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Searched defs:SubReg1 (Results 1 – 8 of 8) sorted by relevance

/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp207 unsigned SubReg1; in isProfitableToTransform() local
299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
H A DAArch64ISelLowering.cpp25742 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); createGPRPairNode() local
25789 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; ReplaceCMP_SWAP_128Results() local
[all...]
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp388 SDValue SubReg1 = CurDAG->getTargetConstant(CSKY::sub32_32, dl, MVT::i32); in createGPRPairNode() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1858 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); createGPRPairNode() local
1869 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); createSRegPairNode() local
1880 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); createDRegPairNode() local
1891 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); createQRegPairNode() local
1903 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); createQuadSRegsNode() local
1918 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); createQuadDRegsNode() local
1933 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); createQuadQRegsNode() local
[all...]
H A DARMISelLowering.cpp10494 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); createGPRPairNode() local
/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp189 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp570 SDValue RC, SubReg0, SubReg1; Select() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1161 unsigned SubReg1 = MI.getOperand(1).getSubReg(); commuteInstructionImpl() local