Searched defs:SubReg0 (Results 1 – 8 of 8) sorted by relevance
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned SubReg0; in isProfitableToTransform() local
298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
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| H A D | AArch64ISelLowering.cpp | 25741 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32); createGPRPairNode() local
[all...] |
| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 387 SDValue SubReg0 = CurDAG->getTargetConstant(CSKY::sub32_0, dl, MVT::i32); in createGPRPairNode() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1857 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); createGPRPairNode() local
1868 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); createSRegPairNode() local
1879 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); createDRegPairNode() local
1890 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); createQRegPairNode() local
1902 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); createQuadSRegsNode() local
1917 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); createQuadDRegsNode() local
1932 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); createQuadQRegsNode() local
[all...] |
| H A D | ARMISelLowering.cpp | 10493 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); createGPRPairNode() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 188 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 252 unsigned SubReg0; createTuple() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 570 SDValue RC, SubReg0, SubReg1; Select() local
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