| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy()
245 unsigned SubReg; in isProfitableToTransform() local
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| H A D | AArch64RegisterInfo.cpp | 278 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), in UpdateCustomCallPreservedMask() local
782 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce()
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| H A D | AArch64ISelDAGToDAG.cpp | 739 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in narrowIfNeeded() local
983 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in Widen() local
1353 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in tryIndexedLoad() local
2110 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in tryBitfieldExtractOp() local
2841 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32); in tryShiftAmountMod() local
3322 auto SubReg = DAG->getTargetConstant(AArch64::dsub, DL, MVT::i32); in extractSubReg() local
3326 auto SubReg = DAG->getTargetConstant(AArch64::zsub, DL, MVT::i32); in extractSubReg() local
3348 auto SubReg = DAG->getTargetConstant(AArch64::dsub, DL, MVT::i32); in insertSubReg() local
3354 auto SubReg = DAG->getTargetConstant(AArch64::zsub, DL, MVT::i32); in insertSubReg() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 196 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
250 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
289 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
338 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
369 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
451 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
473 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
491 unsigned SubReg = *SubRegs; in UpdatePhysRegDefs() local
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| H A D | LiveIntervalCalc.cpp | 68 unsigned SubReg = MO.getSubReg(); in calculate() local
168 unsigned SubReg = MO.getSubReg(); in extendToUses() local
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| H A D | DetectDeadLanes.cpp | 174 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
424 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
457 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
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| H A D | LiveIntervals.cpp | 577 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
791 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
1031 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1458 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1598 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
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| H A D | MachineInstrBundle.cpp | 198 unsigned SubReg = *SubRegs; in finalizeBundle() local
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| H A D | LiveRangeEdit.cpp | 251 unsigned SubReg = MO.getSubReg(); in useIsKill() local
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| H A D | VirtRegMap.cpp | 554 unsigned SubReg = MO.getSubReg(); in rewrite() local
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| H A D | ScheduleDAGInstrs.cpp | 340 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) { in addPhysRegDeps() local
376 unsigned SubReg = MO.getSubReg(); in getLaneMaskForMO() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 319 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg()
324 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg()
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| H A D | SIShrinkInstructions.cpp | 389 Register Reg, unsigned SubReg, in instAccessReg()
409 unsigned Reg, unsigned SubReg, in instReadsReg()
415 unsigned Reg, unsigned SubReg, in instModifiesReg()
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| H A D | SIPreAllocateWWMRegs.cpp | 132 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
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| H A D | SIRegisterInfo.cpp | 1144 Register SubReg = e == 1 in buildSpillLoadStore() local
1321 Register SubReg = in spillSGPR() local
1366 Register SubReg = in spillSGPR() local
1416 Register SubReg = in restoreSGPR() local
1443 Register SubReg = in restoreSGPR() local
2259 unsigned SubReg, in shouldCoalesce()
2382 MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg, in findReachingDef()
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| H A D | SIFormMemoryClauses.cpp | 376 for (unsigned SubReg : KilledIndexes) { in runOnMachineFunction() local
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| H A D | R600OptimizeVectorRegisters.cpp | 196 unsigned SubReg = (*It).first; in RebuildVector() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 543 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
555 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
569 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 254 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
348 for (const auto &SubReg : Map) in computeSubRegs() local
354 for (const auto &SubReg : SubRegs) { in computeSubRegs() local
473 const CodeGenRegister *SubReg; in computeSecondarySubRegs() local
530 for (auto SubReg : NewSubReg->SubRegs) { in computeSecondarySubRegs() local
549 for (auto SubReg : SubRegs) in computeSuperRegs() local
555 for (auto SubReg : SubRegs) { in computeSuperRegs() local
580 for (auto SubReg : SubRegs) in addSubRegsPreOrder() local
2060 CodeGenRegister *SubReg = S.second; in computeRegUnitLaneMasks() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 281 unsigned SubReg, in shouldCoalesce()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 348 const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMIPeephole.cpp | 219 Register SubReg = MovMI->getOperand(1).getReg(); in eliminateZExtSeq() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 1025 unsigned SubReg, in shouldCoalesce()
1115 unsigned SubReg = 0; variable
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 378 unsigned SubReg, in shouldCoalesce()
|