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Searched defs:SubRC (Results 1 – 13 of 13) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
H A DTargetRegisterInfo.cpp202 const TargetRegisterClass *SubRC = getRegClass(It.getID()); getAllocatableClass() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp151 if (const TargetRegisterClass *SubRC = in getRegOpRC() local
1042 if (const TargetRegisterClass *SubRC = foldOperand() local
1903 if (const auto *SubRC = TRI->getSubRegisterClass(CopyInRC, AGPRRegMask)) tryFoldPhiAGPR() local
H A DSIRegisterInfo.cpp2899 getCompatibleSubRegClass(const TargetRegisterClass * SuperRC,const TargetRegisterClass * SubRC,unsigned SubIdx) const getCompatibleSubRegClass() argument
H A DAMDGPUInstructionSelector.cpp250 getSubOperand64(MachineOperand & MO,const TargetRegisterClass & SubRC,unsigned SubIdx) const getSubOperand64() argument
H A DSIInstrInfo.cpp4629 const TargetRegisterClass *SubRC = verifyInstruction() local
H A DSIISelLowering.cpp4923 const TargetRegisterClass *SubRC = EmitInstrWithCustomInserter() local
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp
H A DCompressInstEmitter.cpp173 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
H A DCodeGenRegisters.h
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp126 if (const auto *SubRC = TRI.getCommonSubClass( constrainOperandRegClass() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp3275 const TargetRegisterClass *SubRC = &LoongArch::LSX128RegClass; emitPseudoXVINSGR2VR() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp7052 const TargetRegisterClass *SubRC; genAlternativeCodeSequence() local