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Searched defs:SubIdx (Results 1 – 25 of 38) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp239 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
243 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
263 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
313 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
319 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
331 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
H A DExpandPostRAPseudos.cpp86 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
H A DRegisterCoalescer.cpp1719 unsigned SubIdx) { in updateRegDefsUses()
2311 const unsigned SubIdx; member in __anon3ec327350311::JoinVals
2476 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
2963 bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx, in usesLanes()
H A DTwoAddressInstructionPass.cpp1618 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1672 unsigned SubIdx = MI.getOperand(i+1).getImm(); in eliminateRegSequence() local
H A DTargetInstrInfo.cpp390 unsigned SubIdx, unsigned &Size, in getStackSlotRange()
421 Register DestReg, unsigned SubIdx, in reMaterialize()
H A DMachineCopyPropagation.cpp344 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy() local
H A DTargetRegisterInfo.cpp111 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg()
H A DMachineOperand.cpp77 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg()
H A DMachineInstr.cpp956 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1210 unsigned SubIdx, in substituteRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
H A DARMBaseRegisterInfo.cpp479 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TileConfig.cpp173 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in INITIALIZE_PASS_DEPENDENCY() local
H A DX86InstructionSelector.cpp205 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
743 unsigned SubIdx; in selectTruncOrPtrToInt() local
1156 unsigned SubIdx = X86::NoSubRegister; in emitExtractSubreg() local
1194 unsigned SubIdx = X86::NoSubRegister; in emitInsertSubreg() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp448 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg()
497 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
652 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenRegisters.h384 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
400 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
411 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
H A DCodeGenRegisters.cpp134 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
531 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second); in computeSecondarySubRegs() local
1075 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1840 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
2199 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
2233 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
H A DCodeGenTarget.cpp344 const CodeGenSubRegIndex *SubIdx, in getSuperRegForSubReg()
H A DGlobalISelEmitter.cpp4507 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec); in importExplicitUseRenderer() local
4622 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); in createAndImportSubInstructionRenderer() local
4667 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in createAndImportSubInstructionRenderer() local
4759 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
4820 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
5058 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in inferSuperRegisterClass() local
5301 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); in runOnPattern() local
5385 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in runOnPattern() local
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h365 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
375 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
575 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
H A DTargetInstrInfo.h247 Register &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr()
483 unsigned SubIdx; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp450 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
823 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
884 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in insertHvxElementReg() local
922 unsigned SubIdx; in extractHvxSubvectorReg() local
1045 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; in insertHvxSubvectorReg() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp791 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp746 unsigned SubIdx, unsigned &Size, in getStackSlotRange()

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