| /llvm-project/flang/include/flang/Optimizer/Builder/ |
| H A D | PPCIntrinsicCall.h | 56 Srl, enumerator
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 68 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt() local
2310 const SDValue &Srl = N->getOperand(0); SelectS_BFE() local
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| H A D | SIISelLowering.cpp | 13467 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, performExtractVectorEltCombine() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2059 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); foldMaskAndShiftToExtract() local
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| H A D | X86ISelLowering.cpp | 30261 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, R, LowerRotate() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 470 SDValue Srl = N1.getOperand(0); PreprocessISelDAG() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 13647 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); performTRUNCATECombine() local
13675 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); performANDCombine() local
13997 SDValue Srl = And.getOperand(0); combineVectorMulToSraBitcast() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7004 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); lowerFPTOSI() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17965 SDValue Srl = And.getOperand(0); performMulVectorCmpZeroCombine() local
21905 trySimplifySrlAddToRshrnb(SDValue Srl,SelectionDAG & DAG,const AArch64Subtarget * Subtarget) trySimplifySrlAddToRshrnb() argument
[all...] |
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4828 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); visitSDIVLike() local
[all...] |