| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
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| H A D | SIISelLowering.cpp | 3908 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
7144 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 486 Register SrcVec = Left; in matchINS() local
504 Register DstVec, SrcVec; in applyINS() local
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| /openbsd-src/gnu/llvm/llvm/lib/IR/ |
| H A D | Verifier.cpp | 3029 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
3052 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
3075 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
3097 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2736 Register SrcVec = MI.getOperand(1).getReg(); in bitcastExtractVectorElt() local
2876 Register SrcVec = MI.getOperand(1).getReg(); in bitcastInsertVectorElt() local
3962 Register SrcVec = MI.getOperand(1).getReg(); in fewerElementsVectorExtractInsertVectorElt() local
6661 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
6773 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
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| H A D | CombinerHelper.cpp | 3989 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 629 Value *SrcVec; in foldInsExtFNeg() local
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| /openbsd-src/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 2877 llvm::Value *CodeGenFunction::emitBoolVecConversion(llvm::Value *SrcVec, in emitBoolVecConversion()
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| /openbsd-src/gnu/llvm/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 396 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
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| /openbsd-src/gnu/llvm/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1884 unsigned &Index) -> bool { in LowerConvertLow()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 862 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8505 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
10853 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute()
11124 SDValue SrcVec, IndicesVec; in LowerBUILD_VECTORAsVariablePermute() local
40172 SDValue SrcVec = Op.getOperand(0); in combineX86ShufflesRecursively() local
49342 SDValue SrcVec = N0.getOperand(0); in combineAnd() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14592 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11593 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 24523 SDValue SrcVec = Scalar.getOperand(0); in visitSCALAR_TO_VECTOR() local
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