| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 190 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
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| H A D | AMDGPUInstructionSelector.cpp | 2827 Register SrcVec = normalizeVOP3PMask(Mask, Src0Reg, Src1Reg, ShufMask); in selectG_SHUFFLE_VECTOR() local
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| H A D | SIISelLowering.cpp | 3782 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
6696 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 444 Register SrcVec = Left; in matchINS() local
462 Register DstVec, SrcVec; in applyINS() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | Verifier.cpp | 2925 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2948 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2971 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2994 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2521 Register SrcVec = MI.getOperand(1).getReg(); in bitcastExtractVectorElt() local
2660 Register SrcVec = MI.getOperand(1).getReg(); in bitcastInsertVectorElt() local
3783 Register SrcVec = MI.getOperand(1).getReg(); in fewerElementsVectorExtractInsertVectorElt() local
6233 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
6328 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
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| H A D | CombinerHelper.cpp | 3768 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 337 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 558 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7722 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
9988 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute()
10259 SDValue SrcVec, IndicesVec; in LowerBUILD_VECTORAsVariablePermute() local
44598 SDValue SrcVec = N->getOperand(0).getOperand(0); in combineAnd() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14033 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9127 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
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