| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); RebuildVector() local
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| H A D | SIISelLowering.cpp | 4736 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); emitIndirectDst() local
8705 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, LowerINTRINSIC_WO_CHAIN() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 480 Register SrcVec = Left; matchINS() local
498 Register DstVec, SrcVec; applyINS() local
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| /llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 3292 bool SrcVec = SrcTy->isVectorTy(); visitUIToFPInst() local
3315 bool SrcVec = SrcTy->isVectorTy(); visitSIToFPInst() local
3338 bool SrcVec = SrcTy->isVectorTy(); visitFPToUIInst() local
3360 bool SrcVec = SrcTy->isVectorTy(); visitFPToSIInst() local
[all...] |
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 3035 emitBoolVecConversion(llvm::Value * SrcVec,unsigned NumElementsDst,const llvm::Twine & Name) emitBoolVecConversion() argument
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| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 399 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
[all...] |
| /llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 1513 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1991 __anonf97953580202(SDValue Op, unsigned &Opcode, SDValue &SrcVec, unsigned &Index) LowerConvertLow() argument
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| /llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 643 Value *SrcVec; foldInsExtFNeg() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7417 Register SrcVec = MI.getOperand(1).getReg(); lowerExtractInsertVectorElt() local
7509 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; lowerShuffleVector() local
[all...] |
| H A D | CombinerHelper.cpp | 4125 Register SrcVec = MI.getOperand(1).getReg(); matchExtractVecEltBuildVec() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 862 __anona74f0ac60302(SDValue &SrcVec, SmallVectorImpl<int> &SrcIdx) buildHvxVectorReg() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6078 SDValue SrcVec = SrcExtract.getOperand(0); getFauxShuffleMask() local
8483 createVariablePermute(MVT VT,SDValue SrcVec,SDValue IndicesVec,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) createVariablePermute() argument
8755 SDValue SrcVec, IndicesVec; LowerBUILD_VECTORAsVariablePermute() local
39752 SDValue SrcVec = Op.getOperand(0); combineX86ShufflesRecursively() local
44589 combineExtractFromVectorLoad(SDNode * N,EVT VecVT,SDValue SrcVec,uint64_t Idx,const SDLoc & dl,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI) combineExtractFromVectorLoad() argument
49938 SDValue SrcVec = N0.getOperand(0); combineAnd() local
55989 SDValue SrcVec = Op0.getOperand(0); combineConcatVectorOps() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5033 SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1; lowerShuffleViaVRegSplitting() local
12956 SDValue SrcVec = RHS.getOperand(0); combineBinOpOfExtractToReduceTree() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13065 SDValue SrcVec = V1; LowerVECTOR_SHUFFLE() local
20009 SDValue SrcVec = Elt0->getOperand(0)->getOperand(0); performBuildVectorCombine() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15114 SDValue SrcVec = Ext1.getOperand(0); DAGCombineBuildVector() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 26407 SDValue SrcVec = Scalar.getOperand(0); visitSCALAR_TO_VECTOR() local
[all...] |