| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 405 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); in lowerInlineAsm() local
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| H A D | IRTranslator.cpp | 1478 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); translateExtractValue() local
1495 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); translateInsertValue() local
1692 SmallVector<Register, 3> SrcRegs; translateMemFunc() local
3308 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0)); translateFreeze() local
[all...] |
| H A D | LegalizerHelper.cpp | 1475 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); narrowScalar() local
1633 SmallVector<Register, 2> SrcRegs; narrowScalar() local
1690 SmallVector<Register, 2> SrcRegs, DstRegs; narrowScalar() local
3117 SmallVector<Register, 8> SrcRegs; lowerBitcast() local
3166 SmallVector<Register, 8> SrcRegs; lowerBitcast() local
5956 SmallVector<Register, 2> SrcRegs, DstRegs; narrowScalarExtract() local
6016 SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs; narrowScalarInsert() local
7430 SmallVector<Register, 8> SrcRegs; lowerExtractInsertVectorElt() local
[all...] |
| H A D | CallLowering.cpp | 320 mergeVectorRegsToResultRegs(MachineIRBuilder & B,ArrayRef<Register> DstRegs,ArrayRef<Register> SrcRegs) mergeVectorRegsToResultRegs() argument
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| /llvm-project/bolt/lib/Passes/ |
| H A D | TailDuplication.cpp | 118 BitVector SrcRegs = BitVector(BC.MRI->getNumRegs(), false); in regIsUsed() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 1142 Register SrcRegs[] = {0, 0}; LowerPATCHABLE_EVENT_CALL() local
1242 Register SrcRegs[] = {0, 0, 0}; LowerPATCHABLE_TYPED_EVENT_CALL() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 986 SmallSet<std::pair<Register, unsigned>, 4> SrcRegs; needToBeConvertedToVALU() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1140 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1)); applyMappingLoad() local
2609 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); applyMappingImpl() local
2691 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); applyMappingImpl() local
[all...] |
| H A D | AMDGPULegalizerInfo.cpp | 2798 SmallVector<Register, 8> SrcRegs; legalizeInsertVectorElt() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 819 insertPHI(MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const SmallVectorImpl<RegSubRegPair> & SrcRegs,MachineInstr & OrigPHI) insertPHI() argument
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