| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 179 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
207 unsigned SrcReg2, int64_t ImmValue, in isRedundantFlagInstr() argument
285 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, in optimizeCompareInstr() argument
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 562 matchPushAddSubExt(MachineInstr & MI,MachineRegisterInfo & MRI,Register DstReg,Register SrcReg1,Register SrcReg2) matchPushAddSubExt() argument
588 applyPushAddSubExt(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,bool isSExt,Register DstReg,Register SrcReg1,Register SrcReg2) applyPushAddSubExt() argument
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| H A D | AArch64LegalizerInfo.cpp | 1374 Register SrcReg2 = MI.getOperand(3).getReg(); legalizeICMP() local
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| /llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCCodeEmitter.cpp | 250 MCRegister SrcReg2 = MI.getOperand(1).getReg(); expandLongCondBr() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 442 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
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| H A D | AArch64InstrInfo.cpp | 1175 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
1536 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
6670 Register SrcReg2; genFusedMultiply() local
6732 Register SrcReg2 = MAD->getOperand(3).getReg(); genFNegatedMAD() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 615 Register SrcReg2 = fuseCompareOperations() local
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| H A D | SystemZInstrInfo.cpp | 534 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & Mask,int64_t & Value) const analyzeCompare() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 854 unsigned SrcReg2 = 0; PPCEmitCmp() local
1358 Register SrcReg2 = getRegForValue(I->getOperand(1)); SelectBinaryIntOp() local
[all...] |
| H A D | PPCInstrInfo.cpp | 2348 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & Mask,int64_t & Value) const analyzeCompare() argument
2378 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t Mask,int64_t Value,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
2767 Register SrcReg, SrcReg2; optimizeCmpPostRA() local
5404 Register SrcReg2 = MI->getOperand(2).getReg(); isSignOrZeroExtended() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1713 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & Mask,int64_t & Value) analyzeCompare() argument
1722 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t Mask,int64_t Value,const MachineRegisterInfo * MRI) optimizeCompareInstr() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1415 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp() local
1763 Register SrcReg2 = getRegForValue(I->getOperand(1)); SelectBinaryIntOp() local
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 2789 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
2860 isRedundantFlagInstr(const MachineInstr * CmpI,Register SrcReg,Register SrcReg2,int64_t ImmValue,const MachineInstr * OI,bool & IsThumb1) isRedundantFlagInstr() argument
3015 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
3302 Register SrcReg, SrcReg2; shouldSink() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1431 Register SrcReg, SrcReg2; convertToThreeAddress() local
4766 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
4842 isRedundantFlagInstr(const MachineInstr & FlagI,Register SrcReg,Register SrcReg2,int64_t ImmMask,int64_t ImmValue,const MachineInstr & OI,bool * IsSwapped,int64_t * ImmDelta) const isRedundantFlagInstr() argument
5204 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 670 Register SrcReg, SrcReg2; optimizeCmpInstr() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1881 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & Mask,int64_t & Value) const analyzeCompare() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 9700 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & CmpMask,int64_t & CmpValue) const analyzeCompare() argument
9759 optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int64_t CmpMask,int64_t CmpValue,const MachineRegisterInfo * MRI) const optimizeCompareInstr() argument
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