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Searched defs:SrcLo (Results 1 – 7 of 7) sorted by relevance

/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp56 Register DestLo, DestHi, SrcLo, SrcHi; copyPhysReg() local
H A DAVRISelLowering.cpp295 SDValue SrcLo = LowerShifts() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp709 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); copyPhysReg() local
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); expandPostRAPseudo() local
1411 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); expandPostRAPseudo() local
1423 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); expandPostRAPseudo() local
[all...]
H A DHexagonFrameLowering.cpp1900 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); expandStoreVec2() local
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2962 SDValue SrcLo, SrcHi; SplitVecRes_FP_TO_XINT_SAT() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4776 SDValue SrcLo = DAG.getNode(ISD::AND, DL, MVT::i64, SrcVal, LowerINT_TO_FP() local
[all...]