Home
last modified time | relevance | path

Searched defs:Src1 (Results 1 – 25 of 51) sorted by relevance

123

/openbsd-src/gnu/llvm/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst()
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst()
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst()
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst()
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst()
192 static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2, in executeICMP_EQ()
206 static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2, in executeICMP_NE()
220 static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2, in executeICMP_ULT()
234 static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2, in executeICMP_SLT()
248 static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2, in executeICMP_UGT()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp140 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
156 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
517 MachineOperand &Src1 = SaveExecInst->getOperand(2); in optimizeExecSequence() local
564 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence() local
663 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); in tryRecordVCmpxAndSaveexecSequence() local
H A DSIPeepholeSDWA.cpp547 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
584 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
618 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
664 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
964 if (MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1)) { in isConvertibleToSDWA() local
1021 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA() local
H A DAMDGPUInstCombineIntrinsic.cpp44 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN()
424 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
508 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
537 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
640 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
713 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
H A DR600ExpandSpecialInstrs.cpp149 Register Src1 = in runOnMachineFunction() local
200 unsigned Src1 = 0; in runOnMachineFunction() local
H A DSIShrinkInstructions.cpp227 const MachineOperand &Src1 = MI.getOperand(1); in shrinkScalarCompare() local
393 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma() local
487 MachineOperand *Src1 = &MI.getOperand(2); in shrinkScalarLogicOp() local
820 MachineOperand *Src1 = &MI.getOperand(2); in runOnMachineFunction() local
H A DGCNDPPCombine.cpp302 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local
453 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local
648 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov() local
H A DSIFoldOperands.cpp1042 MachineOperand *Src1 = getImmOrMaterializedImm(MI->getOperand(Src1Idx)); in tryConstantFoldOp() local
1128 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask() local
1169 Register Src1 = MI.getOperand(2).getReg(); in tryFoldZeroHighBits() local
1336 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp() local
1463 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod() local
1497 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod() local
H A DSIInstrInfo.cpp2351 MachineOperand &Src1, in swapSourceModifiers()
2415 MachineOperand &Src1 = MI.getOperand(Src1Idx); in commuteInstructionImpl() local
3118 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); in FoldImmediate() local
3471 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); in convertToThreeAddress() local
3917 const MachineOperand *Src1 in canShrink() local
3942 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink() local
3998 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); in buildShrunkInst() local
4475 const MachineOperand &Src1 = MI.getOperand(Src1Idx); in verifyInstruction() local
4497 const MachineOperand &Src1 = MI.getOperand(Src1Idx); in verifyInstruction() local
5197 MachineOperand &Src1 = MI.getOperand(Src1Idx); in legalizeOperandsVOP2() local
[all …]
H A DSILoadStoreOptimizer.cpp1544 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair() local
1642 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeFlatStorePair() local
1868 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferStorePair() local
2036 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset() local
H A DAMDGPURegBankCombiner.cpp280 MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI); in matchFPMed3ToClamp() local
H A DSIISelLowering.cpp4017 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
4041 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
4081 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
4163 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
4280 Register Src1 = MI.getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
4967 SDValue Src1 = N->getOperand(2); in lowerFCMPIntrinsic() local
5043 SDValue Src1 = N->getOperand(2); in ReplaceNodeResults() local
5055 SDValue Src1 = N->getOperand(2); in ReplaceNodeResults() local
8044 SDValue Src1 = Op.getOperand(5); in LowerINTRINSIC_VOID() local
9004 SDValue Src1 = Op.getOperand(1); in LowerFDIV16() local
[all …]
H A DSIFixSGPRCopies.cpp700 MachineOperand &Src1 = MI.getOperand(Src1Idx); in runOnMachineFunction() local
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp151 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local
168 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local
H A DHexagonGenMux.cpp205 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, in getMuxOpcode()
299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
H A DHexagonConstPropagation.cpp2576 const MachineOperand &Src1 = MI.getOperand(1); in evaluateHexCompare() local
2599 const MachineOperand &Src1, const MachineOperand &Src2, in evaluateHexCompare2()
2633 const MachineOperand &Src1 = MI.getOperand(1); in evaluateHexLogical() local
3027 const MachineOperand &Src1 = MI.getOperand(1); in rewriteHexConstUses() local
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1641 const SrcOp &Src1) { in buildAnd()
1663 const SrcOp &Src1) { in buildXor()
1815 const SrcOp &Src1) { in buildFCopysign()
1841 const SrcOp &Src1) { in buildSMin()
1847 const SrcOp &Src1) { in buildSMax()
1853 const SrcOp &Src1) { in buildUMin()
1859 const SrcOp &Src1) { in buildUMax()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp103 void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1, in computeKnownBitsMin()
597 unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1, in computeNumSignBitsMin()
H A DCSEMIRBuilder.cpp243 const SrcOp &Src1 = SrcOps[1]; in buildInstr() local
H A DLegalizerHelper.cpp1512 Register Src1 = MI.getOperand(1).getReg(); in widenScalarMergeValues() local
4982 auto Src1 = MIRBuilder.buildConcatVectors(PaddedTy, MOps1); in equalizeVectorShuffleLengths() local
5168 Register Src1 = MI.getOperand(NumDefs).getReg(); in narrowScalarAddSub() local
5222 Register Src1 = MI.getOperand(1).getReg(); in narrowScalarMul() local
6390 Register Src1 = MI.getOperand(2).getReg(); in lowerFPOWI() local
6417 Register Src1 = MI.getOperand(2).getReg(); in lowerMinMax() local
6433 Register Src1 = MI.getOperand(2).getReg(); in lowerFCopySign() local
6480 Register Src1 = MI.getOperand(2).getReg(); in lowerFMinNumMaxNum() local
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp173 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForMemcmp()
225 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForStrcmp()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp54 Register Src1) { in PairedCopy()
/openbsd-src/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DInferAddressSpaces.cpp699 Constant *Src1 = CE->getOperand(2); in cloneConstantExprWithNewAddressSpace() local
910 Value *Src1 = Op.getOperand(2); in updateAddressSpace() local
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp56 Register Src1 = MI.getOperand(1).getReg(); in matchExtractVecEltPairwiseAdd() local

123