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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1513 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd()
1535 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, in buildXor()
1543 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot()
1549 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { in buildCTPOP()
1554 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ()
1559 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ_ZERO_UNDEF()
1564 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ()
1569 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ_ZERO_UNDEF()
1574 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) { in buildBSwap()
1669 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, in buildFCopysign()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp43 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN()
278 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
363 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
392 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
494 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
567 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
H A DR600ExpandSpecialInstrs.cpp146 Register Src0 = in runOnMachineFunction() local
198 Register Src0 = in runOnMachineFunction() local
H A DSIPeepholeSDWA.cpp537 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
577 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
645 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
661 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
965 if (MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)) { in isConvertibleToSDWA() local
1018 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA() local
H A DSIShrinkInstructions.cpp69 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
178 const MachineOperand &Src0 = MI.getOperand(0); in shrinkScalarCompare() local
315 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
650 MachineOperand *Src0 = &MI.getOperand(1); in runOnMachineFunction() local
H A DGCNDPPCombine.cpp238 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst() local
540 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov() local
H A DSIFoldOperands.cpp1056 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx)); in tryConstantFoldOp() local
1158 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask() local
1317 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp() local
1433 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod() local
1464 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod() local
H A DSIInstrInfo.cpp2020 MachineOperand &Src0, in swapSourceModifiers()
2085 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
2772 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); in FoldImmediate() local
3073 const MachineOperand *Src0 = &MI.getOperand(Src0Idx); in convertToThreeAddress() local
3085 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
4062 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
4084 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
4158 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
4729 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
5479 Register Src0 = MI.getOperand(1).getReg(); in legalizeOperands() local
[all …]
H A DSIOptimizeExecMasking.cpp428 MachineOperand &Src0 = SaveExecInst->getOperand(1); in runOnMachineFunction() local
H A DAMDGPUPostLegalizerCombiner.cpp211 Register Src0; in matchCvtF32UByteN() local
H A DSILoadStoreOptimizer.cpp1461 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair() local
1616 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair() local
1790 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset() local
H A DSIISelLowering.cpp3890 MachineOperand &Src0 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
3914 MachineOperand &Src0 = MI.getOperand(1); in EmitInstrWithCustomInserter() local
3962 MachineOperand &Src0 = MI.getOperand(1); in EmitInstrWithCustomInserter() local
4025 MachineOperand &Src0 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
4126 Register Src0 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
4720 SDValue Src0 = N->getOperand(1); in lowerFCMPIntrinsic() local
4796 SDValue Src0 = N->getOperand(1); in ReplaceNodeResults() local
4808 SDValue Src0 = N->getOperand(1); in ReplaceNodeResults() local
6607 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator; in LowerINTRINSIC_WO_CHAIN() local
7543 SDValue Src0 = Op.getOperand(4); in LowerINTRINSIC_VOID() local
[all …]
H A DSIFixSGPRCopies.cpp720 MachineOperand &Src0 = MI.getOperand(Src0Idx); in runOnMachineFunction() local
H A DAMDGPUPromoteAlloca.cpp962 Value *Src0 = CI->getOperand(0); in handleAlloca() local
H A DAMDGPUInstructionSelector.cpp603 Register Src0 = MI.getOperand(1).getReg(); in selectG_BUILD_VECTOR_TRUNC() local
763 Register Src0 = MI.getOperand(2).getReg(); in selectInterpP1F16() local
884 Register Src0 = ChooseDenom != 0 ? Numer : Denom; in selectDivScale() local
2775 static Register normalizeVOP3PMask(int NewMask[2], Register Src0, Register Src1, in normalizeVOP3PMask()
H A DAMDGPULegalizerInfo.cpp2175 Register Src0 = MI.getOperand(1).getReg(); in legalizeShuffleVector() local
2550 Register Src0 = MI.getOperand(1).getReg(); in legalizeFPow() local
2658 Register Src0 = MI.getOperand(1).getReg(); in legalizeBuildVector() local
H A DR600InstrInfo.cpp1304 MachineOperand &Src0 = MI->getOperand( in buildSlotOfVectorInstruction() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp98 void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1, in computeKnownBitsMin()
508 unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1, in computeNumSignBitsMin()
H A DCSEMIRBuilder.cpp199 const SrcOp &Src0 = SrcOps[0]; in buildInstr() local
H A DLegalizerHelper.cpp5961 Register Src0 = MI.getOperand(1).getReg(); in lowerFPOWI() local
5988 Register Src0 = MI.getOperand(1).getReg(); in lowerMinMax() local
6004 Register Src0 = MI.getOperand(1).getReg(); in lowerFCopySign() local
6051 Register Src0 = MI.getOperand(1).getReg(); in lowerFMinNumMaxNum() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp150 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedLoad() local
420 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedGather() local
H A DInferAddressSpaces.cpp656 Constant *Src0 = CE->getOperand(1); in cloneConstantExprWithNewAddressSpace() local
842 Value *Src0 = Op.getOperand(1); in updateAddressSpace() local
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGBuiltin.cpp444 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitUnaryMaybeConstrainedFPBuiltin() local
461 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitBinaryMaybeConstrainedFPBuiltin() local
479 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitTernaryMaybeConstrainedFPBuiltin() local
517 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitUnaryBuiltin() local
527 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitBinaryBuiltin() local
538 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitTernaryBuiltin() local
550 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitFPIntBuiltin() local
563 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitMaybeConstrainedFPToIntRoundBuiltin() local
15555 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); in EmitAMDGPUBuiltinExpr() local
15624 Value *Src0 = EmitScalarExpr(E->getArg(0)); in EmitAMDGPUBuiltinExpr() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp4298 auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, in visitMaskedStore()
4299 MaybeAlign &Alignment) { in visitMaskedStore()
4315 SDValue Src0 = getValue(Src0Operand); in visitMaskedStore() local
4406 SDValue Src0 = getValue(I.getArgOperand(0)); in visitMaskedScatter() local
4462 auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, in visitMaskedLoad()
4463 MaybeAlign &Alignment) { in visitMaskedLoad()
4479 SDValue Src0 = getValue(Src0Operand); in visitMaskedLoad() local
4522 SDValue Src0 = getValue(I.getArgOperand(3)); in visitMaskedGather() local

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