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Searched defs:ShiftAmt (Results 1 – 25 of 62) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Analysis/
H A DDemandedBits.cpp130 uint64_t ShiftAmt = SA->urem(BitWidth); in determineLiveOperandBits() local
178 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); in determineLiveOperandBits() local
195 uint64_t ShiftAmt in determineLiveOperandBits() local
209 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); determineLiveOperandBits() local
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H A DConstantFolding.cpp218 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); in FoldBitCast() local
272 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); in FoldBitCast() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h805 ashr(unsigned ShiftAmt) ashr() argument
812 ashrInPlace(unsigned ShiftAmt) ashrInPlace() argument
836 lshrInPlace(unsigned ShiftAmt) lshrInPlace() argument
886 ashr(const APInt & ShiftAmt) ashr() argument
898 lshr(const APInt & ShiftAmt) lshr() argument
910 shl(const APInt & ShiftAmt) shl() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Support/
H A DKnownBits.cpp189 __anon9671e40d0402(const KnownBits &LHS, unsigned ShiftAmt) shl() argument
254 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; shl() local
274 __anon9671e40d0502(const KnownBits &LHS, unsigned ShiftAmt) lshr() argument
300 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; lshr() local
320 __anon9671e40d0602(const KnownBits &LHS, unsigned ShiftAmt) ashr() argument
348 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; ashr() local
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H A DAPInt.cpp1026 void APInt::ashrSlowCase(unsigned ShiftAmt) { in ashrSlowCase() argument
1075 void APInt::lshrSlowCase(unsigned ShiftAmt) { in lshrSlowCase() argument
1087 void APInt::shlSlowCase(unsigned ShiftAmt) { in shlSlowCase() argument
2257 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); toString() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DVNCoercion.cpp140 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedValue() - in coerceAvailableValueToLoadType() local
320 unsigned ShiftAmt; in getStoreValueForLoadHelper() local
/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp650 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); SimplifyDemandedUseBits() local
701 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); SimplifyDemandedUseBits() local
771 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); SimplifyDemandedUseBits() local
983 uint64_t ShiftAmt = SA->urem(BitWidth); SimplifyDemandedUseBits() local
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H A DInstCombineCasts.cpp1046 uint64_t ShiftAmt = Amt->getZExtValue(); canEvaluateZExtd() local
1300 unsigned ShiftAmt = KnownZeroMask.countr_zero(); transformSExtICmp() local
1314 unsigned ShiftAmt = KnownZeroMask.countl_zero(); transformSExtICmp() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare() local
H A DAArch64ExpandImm.cpp69 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
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H A DAArch64ISelDAGToDAG.cpp584 unsigned ShiftAmt; SelectArithImmed() local
2701 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); getUsefulBitsFromOrWithShiftedReg() local
2709 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); getUsefulBitsFromOrWithShiftedReg() local
3606 SDValue ShiftAmt = N->getOperand(1); tryShiftAmountMod() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp440 generateTwoRegInstSeq(int64_t Val,const MCSubtargetInfo & STI,unsigned & ShiftAmt,unsigned & AddOpc) generateTwoRegInstSeq() argument
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp279 auto ShiftAmt = buildLCMMergePieces() local
1815 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); widenScalarMergeValues() local
1945 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); widenScalarUnmergeValues() local
2464 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); widenScalar() local
3413 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); lowerLoad() local
3513 auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, LargeSplitSize); lowerStore() local
3665 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); lower() local
5117 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); narrowScalarShift() local
6928 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); lowerFCopySign() local
6933 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); lowerFCopySign() local
7068 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); lowerMergeValues() local
7109 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); lowerUnmergeValues() local
7350 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); lowerExtract() local
7435 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); lowerInsert() local
7665 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); lowerBswap() local
7675 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); lowerBswap() local
7772 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); lowerSMULH_UMULH() local
8031 auto ShiftAmt = lowerAbsToAddXor() local
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H A DLoadStoreOpt.cpp650 int64_t ShiftAmt; getTruncStoreByteOffset() local
H A DCombinerHelper.cpp1911 int64_t ShiftAmt = MaybeShiftAmtVal->getSExtValue(); matchCombineShlOfExtend() local
1927 auto ShiftAmt = Builder.buildConstant(ExtSrcTy, ShiftAmtVal); applyCombineShlOfExtend() local
2032 unsigned ShiftAmt = Dst0Ty.getSizeInBits(); matchCombineUnmergeConstant() local
2264 unsigned ShiftAmt; tryCombineShiftToUnmerge() local
2577 Register ShiftAmt = ShiftMI->getOperand(2).getReg(); applyCombineTruncOfShift() local
3110 int64_t ShiftAmt; applyAshShlToSextInreg() local
5307 auto ShiftAmt = applyUMulHToLShr() local
6053 std::optional<ValueAndVReg> ShiftAmt; matchTruncLshrBuildVectorFold() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2067 unsigned ShiftAmt = Shift.getConstantOperandVal(1); foldMaskedShiftToScaledMask() local
2140 unsigned ShiftAmt = Shift.getConstantOperandVal(1); foldMaskAndShiftToScale() local
2238 unsigned ShiftAmt = Shift.getConstantOperandVal(1); foldMaskedShiftToBEXTR() local
2313 uint64_t ShiftAmt = N.getConstantOperandVal(1); matchIndexRecursively() local
3819 __anon4a8bd31b1002(SDValue ShiftAmt, unsigned Bitwidth) matchBitExtract() argument
3990 SDValue ShiftAmt = X.getOperand(1); matchBitExtract() local
4229 SDValue ShiftAmt = OrigShiftAmt; tryShiftAmountMod() local
5902 unsigned ShiftAmt; Select() local
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H A DX86InstCombineIntrinsic.cpp287 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth)); simplifyX86immShift() local
2074 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); instCombineIntrinsic() local
2117 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); instCombineIntrinsic() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp345 int64_t ShiftAmt; matchCvtF32UByteN() local
H A DR600ISelLowering.cpp1065 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, lowerPrivateTruncStore() local
1294 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, lowerPrivateExtLoad() local
H A DAMDGPUISelDAGToDAG.cpp70 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt() local
3350 ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); SelectSWMMACIndex8() local
3369 ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); SelectSWMMACIndex16() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp185 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1921 insertMultibyteShift(MachineInstr & MI,MachineBasicBlock * BB,MutableArrayRef<std::pair<Register,int>> Regs,ISD::NodeType Opc,int64_t ShiftAmt) insertMultibyteShift() argument
2193 int64_t ShiftAmt = MI.getOperand(4).getImm(); insertWideShift() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp222 unsigned ShiftAmt, AddOpc; selectImm() local
2340 uint64_t ShiftAmt = 0; SelectAddrRegRegScale() local
2688 __anon6ef9331d0402(SDValue N, unsigned ShiftAmt) selectSExtBits() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1611 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1); executeBitCastInst() local
1627 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1); executeBitCastInst() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1605 uint64_t ShiftAmt = ShiftC->getZExtValue(); SimplifyDemandedBits() local
2333 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ExVTBits, dl, SimplifyDemandedBits() local
4095 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); optimizeSetCCOfSignedTruncationCheck() local
8837 unsigned ShiftAmt = BitWidth - Log2_32(BitWidth); CTTZTableLookup() local
10485 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy); expandMULO() local
10517 SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits(), dl, expandMULO() local
10592 SDValue ShiftAmt = DAG.getConstant( expandMULO() local
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