| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 66 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in generateInstSeqImpl() local
86 unsigned ShiftAmount = countLeadingZeros((uint64_t)Val); in generateInstSeq() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 307 uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second); in eliminateFrameIndex() local
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| H A D | RISCVFrameLowering.cpp | 499 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
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| H A D | RISCVInstrInfo.cpp | 1374 uint32_t ShiftAmount = Log2_32(NumOfVReg); in getVLENFactoredAmount() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 1004 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros(); in instCombineIntrinsic() local
1049 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros(); in instCombineIntrinsic() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 391 unsigned ShiftAmount; member
1884 unsigned ShiftAmount = 0, in CreateReg()
1903 unsigned ShiftAmount = 0, in CreateVectorReg()
1948 unsigned ShiftAmount, in CreateShiftedImm()
2725 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1043 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
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| H A D | TargetLowering.cpp | 6336 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
7337 SDValue ShiftAmount = in scalarizeVectorLoad() local
7422 SDValue ShiftAmount = in scalarizeVectorStore() local
7599 SDValue ShiftAmount = in expandUnalignedLoad() local
7713 SDValue ShiftAmount = DAG.getConstant( in expandUnalignedStore() local
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| H A D | LegalizeIntegerTypes.cpp | 823 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT); in PromoteIntRes_ADDSUBSHLSAT() local
3489 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); in ExpandIntRes_MULFIX() local
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| H A D | LegalizeDAG.cpp | 1584 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN() local
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| H A D | DAGCombiner.cpp | 10765 SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT); in foldExtendedSignBitTest() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 6664 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6685 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6702 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
6707 unsigned ShiftAmount = C->countLeadingZeros() - 1; in setLimitsForBinOp() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 967 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 268 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1857 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCasts.cpp | 498 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5255 const MCExpr *ShiftAmount; in parsePKHImm() local
5338 const MCExpr *ShiftAmount; in parseShifterImm() local
5400 const MCExpr *ShiftAmount; in parseRotImm() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10963 uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1); in shouldReduceLoadWidth() local
12539 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf()
12927 uint64_t ShiftAmount = Shift.getConstantOperandVal(1); in performVectorTruncateCombine() local
13576 int64_t ShiftAmount; in tryCombineShiftImm() local
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| H A D | AArch64ISelDAGToDAG.cpp | 2392 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2814 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); in loadImmediate() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6624 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); in lowerAddSubSatToAddoSubo() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5274 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32); in getSegmentAperture() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 16883 unsigned ShiftAmount = TrueConst->logBase2(); in PerformCMOVCombine() local
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