| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegUsageInfoCollector.cpp | 138 BitVector SavedRegs; in runOnMachineFunction() local
196 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { in computeCalleeSavedRegs()
|
| H A D | TargetFrameLoweringImpl.cpp | 79 BitVector &SavedRegs, in determineCalleeSaves()
|
| H A D | ShrinkWrap.cpp | 167 BitVector SavedRegs; in getCurrentCSRs() local
|
| H A D | PrologEpilogInserter.cpp | 384 const BitVector &SavedRegs, in assignCalleeSavedSpillSlots()
607 BitVector SavedRegs; in spillCalleeSavedRegs() local
|
| H A D | RegisterScavenging.cpp | 788 BitVector SavedRegs; in runOnMachineFunction() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFFrameLowering.cpp | 32 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiFrameLowering.cpp | 198 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 160 BitVector &SavedRegs, in determineCalleeSaves()
|
| H A D | MipsSEFrameLowering.cpp | 853 static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs, in setAliasRegs()
861 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 369 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | Taint.cpp | 134 const TaintedSubRegions *SavedRegs = State->get<DerivedSymTaint>(ParentSym); in addPartialTaint() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 487 BitVector &SavedRegs, in determineCalleeSaves()
|
| H A D | VEISelLowering.cpp | 2404 const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs(); in emitSjLjDispatchBlock() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerSGPRSpills.cpp | 206 BitVector SavedRegs; in spillCalleeSavedRegs() local
|
| H A D | SIFrameLowering.cpp | 1208 BitVector &SavedRegs, in determineCalleeSavesSGPR()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRFrameLowering.cpp | 403 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 89 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 528 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kFrameLowering.cpp | 777 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 1700 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) { in checkNumAlignedDPRCS2Regs()
1754 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 134 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 771 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 1278 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS]; member in __anon0be7a23a0411::DarwinX86AsmBackend
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 1961 BitVector &SavedRegs, in determineCalleeSaves()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 2665 BitVector &SavedRegs, in determineCalleeSaves()
|