1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * IntelVersion: 1.41 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 #ifndef _E1000_ICH8LAN_H_ 30 #define _E1000_ICH8LAN_H_ 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define ICH_FLASH_GFPREG 0x0000 37 #define ICH_FLASH_HSFSTS 0x0004 38 #define ICH_FLASH_HSFCTL 0x0006 39 #define ICH_FLASH_FADDR 0x0008 40 #define ICH_FLASH_FDATA0 0x0010 41 42 /* Requires up to 10 seconds when MNG might be accessing part. */ 43 #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 44 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 45 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 46 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 47 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 48 49 #define ICH_CYCLE_READ 0 50 #define ICH_CYCLE_WRITE 2 51 #define ICH_CYCLE_ERASE 3 52 53 #define FLASH_GFPREG_BASE_MASK 0x1FFF 54 #define FLASH_SECTOR_ADDR_SHIFT 12 55 56 #define ICH_FLASH_SEG_SIZE_256 256 57 #define ICH_FLASH_SEG_SIZE_4K 4096 58 #define ICH_FLASH_SEG_SIZE_8K 8192 59 #define ICH_FLASH_SEG_SIZE_64K 65536 60 #define ICH_FLASH_SECTOR_SIZE 4096 61 62 #define ICH_FLASH_REG_MAPSIZE 0x00A0 63 64 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 65 #define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ 66 /* FW established a valid mode */ 67 #define E1000_ICH_FWSM_FW_VALID 0x00008000 68 69 #define E1000_ICH_MNG_IAMT_MODE 0x2 70 71 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 72 (ID_LED_OFF1_OFF2 << 8) | \ 73 (ID_LED_OFF1_ON2 << 4) | \ 74 (ID_LED_DEF1_DEF2)) 75 76 #define E1000_ICH_NVM_SIG_WORD 0x13 77 #define E1000_ICH_NVM_SIG_MASK 0xC000 78 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 79 #define E1000_ICH_NVM_SIG_VALUE 0x80 80 81 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 82 83 #define E1000_FEXTNVM_SW_CONFIG 1 84 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ 85 86 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 87 88 #define E1000_ICH_RAR_ENTRIES 7 89 90 #define PHY_PAGE_SHIFT 5 91 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 92 ((reg) & MAX_PHY_REG_ADDRESS)) 93 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 94 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 95 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ 96 #define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ 97 98 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 99 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 100 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 101 #define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 102 103 /* PHY Wakeup Registers and defines */ 104 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 105 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 106 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 107 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 108 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 109 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 110 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 111 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 112 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 113 114 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 115 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 116 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 117 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 118 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 119 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 120 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 121 122 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 123 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 124 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 125 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 126 #define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ 127 #define HV_SCC_LOWER PHY_REG(778, 17) 128 #define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ 129 #define HV_ECOL_LOWER PHY_REG(778, 19) 130 #define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ 131 #define HV_MCC_LOWER PHY_REG(778, 21) 132 #define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ 133 #define HV_LATECOL_LOWER PHY_REG(778, 24) 134 #define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 135 #define HV_COLC_LOWER PHY_REG(778, 26) 136 #define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 137 #define HV_DC_LOWER PHY_REG(778, 28) 138 #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 139 #define HV_TNCRS_LOWER PHY_REG(778, 30) 140 141 /* PCH Flow Control Refresh Timer Value */ 142 #define E1000_FCRTV_PCH 0x05F40 143 144 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 145 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 146 147 /* SMBus Address Phy Register */ 148 #define HV_SMB_ADDR PHY_REG(768, 26) 149 #define HV_SMB_ADDR_PEC_EN 0x0200 150 #define HV_SMB_ADDR_VALID 0x0080 151 152 /* Strapping Option Register - RO */ 153 #define E1000_STRAP 0x0000C 154 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 155 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 156 157 /* OEM Bits Phy Register */ 158 #define HV_OEM_BITS PHY_REG(768, 25) 159 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 160 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 161 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 162 /* Phy address bit from LCD Config word */ 163 #define LCD_CFG_PHY_ADDR_BIT 0x0020 164 165 /* SW Semaphore flag timeout in milliseconds */ 166 #define SW_FLAG_TIMEOUT 400 167 168 /* 169 * Additional interrupts need to be handled for ICH family: 170 * DSW = The FW changed the status of the DISSW bit in FWSM 171 * PHYINT = The LAN connected device generates an interrupt 172 * EPRST = Manageability reset event 173 */ 174 #define IMS_ICH_ENABLE_MASK (\ 175 E1000_IMS_DSW | \ 176 E1000_IMS_PHYINT | \ 177 E1000_IMS_EPRST) 178 179 /* Additional interrupt register bit definitions */ 180 #define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */ 181 #define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ 182 #define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ 183 184 /* Security Processing bit Indication */ 185 #define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 186 #define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 187 #define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 188 #define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 189 #define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 190 191 192 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 193 bool state); 194 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 195 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 196 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw); 197 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 198 s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config); 199 200 #ifdef __cplusplus 201 } 202 #endif 203 204 #endif /* _E1000_ICH8LAN_H_ */ 205