1 /* $NetBSD: sunxi_hdmireg.h,v 1.1 2018/04/03 12:52:16 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #define SUNXI_HDMI_VERSION_ID_REG 0x0000 34 #define SUNXI_HDMI_CTRL_REG 0x0004 35 #define SUNXI_HDMI_INT_STATUS_REG 0x0008 36 #define SUNXI_HDMI_HPD_REG 0x000c 37 #define SUNXI_HDMI_VID_CTRL_REG 0x0010 38 #define SUNXI_HDMI_VID_TIMING_0_REG 0x0014 39 #define SUNXI_HDMI_VID_TIMING_1_REG 0x0018 40 #define SUNXI_HDMI_VID_TIMING_2_REG 0x001c 41 #define SUNXI_HDMI_VID_TIMING_3_REG 0x0020 42 #define SUNXI_HDMI_VID_TIMING_4_REG 0x0024 43 #define SUNXI_HDMI_AUD_CTRL_REG 0x0040 44 #define SUNXI_HDMI_ADMA_CTRL_REG 0x0044 45 #define SUNXI_HDMI_AUD_FMT_REG 0x0048 46 #define SUNXI_HDMI_AUD_PCM_CTRL_REG 0x004c 47 #define SUNXI_HDMI_AUD_CTS_REG 0x0050 48 #define SUNXI_HDMI_AUD_N_REG 0x0054 49 #define SUNXI_HDMI_AUD_CH_STATUS0_REG 0x0058 50 #define SUNXI_HDMI_AUD_CH_STATUS1_REG 0x005c 51 #define SUNXI_HDMI_AVI_INFO_PKT_REG 0x0080 52 #define SUNXI_HDMI_AUD_INFO_PKT_REG 0x00a0 53 #define SUNXI_HDMI_ACP_PKT_REG 0x00c0 54 #define SUNXI_HDMI_GP_PKT0_REG 0x00e0 55 #define SUNXI_HDMI_GP_PKT1_REG 0x00e0 56 #define SUNXI_HDMI_PAD_CTRL0_REG 0x0200 57 #define SUNXI_HDMI_PAD_CTRL1_REG 0x0204 58 #define SUNXI_HDMI_PLL_CTRL_REG 0x0208 59 #define SUNXI_HDMI_PLL_DBG0_REG 0x020c 60 #define SUNXI_HDMI_PLL_DBG1_REG 0x0210 61 #define SUNXI_HDMI_HPD_CEC_REG 0x0214 62 #define SUNXI_HDMI_SPD_PKT_REG 0x0240 63 #define SUNXI_HDMI_PKT_CTRL0_REG 0x02f0 64 #define SUNXI_HDMI_PKT_CTRL1_REG 0x02f4 65 #define SUNXI_HDMI_DBG4_REG 0x0310 66 #define SUNXI_HDMI_AUX_TX_FIFO_REG 0x0400 67 #define SUNXI_HDMI_DDC_CTRL_REG 0x0500 68 #define SUNXI_HDMI_DDC_SLAVE_ADDR_REG 0x0504 69 #define SUNXI_HDMI_DDC_INT_MASK_REG 0x0508 70 #define SUNXI_HDMI_DDC_INT_STATUS_REG 0x050c 71 #define SUNXI_HDMI_DDC_FIFO_CTRL_REG 0x0510 72 #define SUNXI_HDMI_DDC_FIFO_STATUS_REG 0x0514 73 #define SUNXI_HDMI_DDC_FIFO_ACCESS_REG 0x0518 74 #define SUNXI_HDMI_DDC_BYTE_COUNTER_REG 0x051c 75 #define SUNXI_HDMI_DDC_COMMAND_REG 0x0520 76 #define SUNXI_HDMI_DDC_EX_REG 0x0524 77 #define SUNXI_HDMI_DDC_CLOCK_REG 0x0528 78 #define SUNXI_HDMI_DDC_DBG_REG 0x0540 79 80 #define SUNXI_HDMI_VERSION_ID_H __BITS(31,16) 81 #define SUNXI_HDMI_VERSION_ID_L __BITS(15,0) 82 83 #define SUNXI_HDMI_CTRL_MODULE_EN __BIT(31) 84 #define SUNXI_HDMI_CTRL_HDCP_EN __BIT(30) 85 #define SUNXI_HDMI_CTRL_CLR_AVMUTE __BIT(1) 86 #define SUNXI_HDMI_CTRL_SET_AVMUTE __BIT(0) 87 88 #define SUNXI_HDMI_HPD_HOTPLUG_DET __BIT(0) 89 90 #define SUNXI_HDMI_VID_CTRL_VIDEO_EN __BIT(31) 91 #define SUNXI_HDMI_VID_CTRL_HDMI_MODE __BIT(30) 92 #define SUNXI_HDMI_VID_CTRL_HDMI_MODE_DVI 0 93 #define SUNXI_HDMI_VID_CTRL_HDMI_MODE_HDMI 1 94 #define SUNXI_HDMI_VID_CTRL_SRC_SEL __BIT(5) 95 #define SUNXI_HDMI_VID_CTRL_SRC_SEL_RGB 0 96 #define SUNXI_HDMI_VID_CTRL_SRC_SEL_CBGEN 1 97 #define SUNXI_HDMI_VID_CTRL_OUTPUT_FMT __BIT(4) 98 #define SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_PROGRESS 0 99 #define SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE 1 100 #define SUNXI_HDMI_VID_CTRL_COLOR_MODE __BITS(3,2) 101 #define SUNXI_HDMI_VID_CTRL_COLOR_MODE_24 0 102 #define SUNXI_HDMI_VID_CTRL_COLOR_MODE_30 1 103 #define SUNXI_HDMI_VID_CTRL_COLOR_MODE_36 2 104 #define SUNXI_HDMI_VID_CTRL_COLOR_MODE_48 3 105 #define SUNXI_HDMI_VID_CTRL_REPEATER_SEL __BITS(1,0) 106 #define SUNXI_HDMI_VID_CTRL_REPEATER_SEL_NORMAL 0 107 #define SUNXI_HDMI_VID_CTRL_REPEATER_SEL_2X 1 108 #define SUNXI_HDMI_VID_CTRL_REPEATER_SEL_4X 2 109 110 #define SUNXI_HDMI_VID_TIMING_0_ACT_V __BITS(27,16) 111 #define SUNXI_HDMI_VID_TIMING_0_ACT_H __BITS(11,0) 112 113 #define SUNXI_HDMI_VID_TIMING_1_VBP __BITS(27,16) 114 #define SUNXI_HDMI_VID_TIMING_1_HBP __BITS(11,0) 115 116 #define SUNXI_HDMI_VID_TIMING_2_VFP __BITS(27,16) 117 #define SUNXI_HDMI_VID_TIMING_2_HFP __BITS(11,0) 118 119 #define SUNXI_HDMI_VID_TIMING_3_VSPW __BITS(27,16) 120 #define SUNXI_HDMI_VID_TIMING_3_HSPW __BITS(11,0) 121 122 #define SUNXI_HDMI_VID_TIMING_4_TX_CLOCK __BITS(25,16) 123 #define SUNXI_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL 0x3e0 124 #define SUNXI_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL __BIT(1) 125 #define SUNXI_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL __BIT(0) 126 127 #define SUNXI_HDMI_PAD_CTRL0_BIAS __BIT(31) 128 #define SUNXI_HDMI_PAD_CTRL0_LDOCEN __BIT(30) 129 #define SUNXI_HDMI_PAD_CTRL0_LD0DEN __BIT(29) 130 #define SUNXI_HDMI_PAD_CTRL0_PWENC __BIT(28) 131 #define SUNXI_HDMI_PAD_CTRL0_PWEND __BIT(27) 132 #define SUNXI_HDMI_PAD_CTRL0_PWENG __BIT(26) 133 #define SUNXI_HDMI_PAD_CTRL0_CKEN __BIT(25) 134 #define SUNXI_HDMI_PAD_CTRL0_SEN __BIT(24) 135 #define SUNXI_HDMI_PAD_CTRL0_TXEN __BIT(23) 136 #define SUNXI_HDMI_PAD_CTRL0_AUTOSYNC_DIS __BIT(22) 137 #define SUNXI_HDMI_PAD_CTRL0_LSB_MSB __BIT(21) 138 139 #define SUNXI_HDMI_PAD_CTRL1_AMP_OPT __BIT(23) 140 #define SUNXI_HDMI_PAD_CTRL1_AMPCK_OPT __BIT(22) 141 #define SUNXI_HDMI_PAD_CTRL1_DMP_OPT __BIT(21) 142 #define SUNXI_HDMI_PAD_CTRL1_EMP_OPT __BIT(20) 143 #define SUNXI_HDMI_PAD_CTRL1_EMPCK_OPT __BIT(19) 144 #define SUNXI_HDMI_PAD_CTRL1_PWSCK __BIT(18) 145 #define SUNXI_HDMI_PAD_CTRL1_PWSDT __BIT(17) 146 #define SUNXI_HDMI_PAD_CTRL1_REG_CSMPS __BIT(16) 147 #define SUNXI_HDMI_PAD_CTRL1_REG_DEN __BIT(15) 148 #define SUNXI_HDMI_PAD_CTRL1_REG_DENCK __BIT(14) 149 #define SUNXI_HDMI_PAD_CTRL1_REG_PLRCK __BIT(13) 150 #define SUNXI_HDMI_PAD_CTRL1_REG_EMP __BITS(12,10) 151 #define SUNXI_HDMI_PAD_CTRL1_REG_CD __BITS(9,8) 152 #define SUNXI_HDMI_PAD_CTRL1_REG_CKSS __BITS(7,6) 153 #define SUNXI_HDMI_PAD_CTRL1_REG_AMP __BITS(5,3) 154 #define SUNXI_HDMI_PAD_CTRL1_REG_PLR __BITS(2,0) 155 156 #define SUNXI_HDMI_PLL_CTRL_PLL_EN __BIT(31) 157 #define SUNXI_HDMI_PLL_CTRL_BWS __BIT(30) 158 #define SUNXI_HDMI_PLL_CTRL_HV_IS_33 __BIT(29) 159 #define SUNXI_HDMI_PLL_CTRL_LDO1_EN __BIT(28) 160 #define SUNXI_HDMI_PLL_CTRL_LDO2_EN __BIT(27) 161 #define SUNXI_HDMI_PLL_CTRL_S6P25_7P5 __BIT(26) 162 #define SUNXI_HDMI_PLL_CTRL_SDIV2 __BIT(25) 163 #define SUNXI_HDMI_PLL_CTRL_SINT_FRAC __BIT(24) 164 #define SUNXI_HDMI_PLL_CTRL_VCO_GAIN_EN __BIT(23) 165 #define SUNXI_HDMI_PLL_CTRL_VCO_GAIN __BITS(22,20) 166 #define SUNXI_HDMI_PLL_CTRL_S __BITS(19,17) 167 #define SUNXI_HDMI_PLL_CTRL_CP_S __BITS(16,12) 168 #define SUNXI_HDMI_PLL_CTRL_CS __BITS(11,8) 169 #define SUNXI_HDMI_PLL_CTRL_PREDIV __BITS(7,4) 170 #define SUNXI_HDMI_PLL_CTRL_VCO_S __BITS(3,0) 171 172 #define SUNXI_HDMI_AUD_CTRL_EN __BIT(31) 173 #define SUNXI_HDMI_AUD_CTRL_RST __BIT(30) 174 175 #define SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE __BIT(31) 176 #define SUNXI_HDMI_ADMA_CTRL_DMA_REQ_CTRL __BITS(25,24) 177 #define SUNXI_HDMI_ADMA_CTRL_SRC_DMA_SAMPLE_RATE __BIT(19) 178 #define SUNXI_HDMI_ADMA_CTRL_SRC_SAMPLE_LAYOUT __BIT(18) 179 #define SUNXI_HDMI_ADMA_CTRL_SRC_WORD_LEN __BITS(17,16) 180 #define SUNXI_HDMI_ADMA_CTRL_FIFO_CLEAR __BIT(15) 181 #define SUNXI_HDMI_ADMA_CTRL_DATA_SEL __BIT(0) 182 183 #define SUNXI_HDMI_AUD_FMT_SRC_SEL __BIT(31) 184 #define SUNXI_HDMI_AUD_FMT_SEL __BITS(26,24) 185 #define SUNXI_HDMI_AUD_FMT_DSD_FMT __BIT(4) 186 #define SUNXI_HDMI_AUD_FMT_LAYOUT __BIT(3) 187 #define SUNXI_HDMI_AUD_FMT_SRC_CH_CFG __BITS(2,0) 188 189 #define SUNXI_HDMI_AUD_CH_STATUS0_CHNL_BIT1 __BITS(31,30) 190 #define SUNXI_HDMI_AUD_CH_STATUS0_CLK_ACCUR __BITS(29,28) 191 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ __BITS(27,24) 192 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_44_1 0 193 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_48 2 194 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_32 3 195 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_88_2 8 196 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_96 10 197 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_176_4 12 198 #define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_192 14 199 #define SUNXI_HDMI_AUD_CH_STATUS0_CH_NUM __BITS(23,20) 200 #define SUNXI_HDMI_AUD_CH_STATUS0_SOURCE_NUM __BITS(19,16) 201 #define SUNXI_HDMI_AUD_CH_STATUS0_CATEGORY_CODE __BITS(15,8) 202 #define SUNXI_HDMI_AUD_CH_STATUS0_MODE __BITS(7,6) 203 #define SUNXI_HDMI_AUD_CH_STATUS0_EMPHASIS __BITS(5,3) 204 #define SUNXI_HDMI_AUD_CH_STATUS0_CP __BIT(2) 205 #define SUNXI_HDMI_AUD_CH_STATUS0_DATA_TYPE __BIT(1) 206 #define SUNXI_HDMI_AUD_CH_STATUS0_APP_TYPE __BIT(0) 207 208 #define SUNXI_HDMI_AUD_CH_STATUS1_CGMS_A __BITS(9,8) 209 #define SUNXI_HDMI_AUD_CH_STATUS1_ORIGINAL_FS __BITS(7,4) 210 #define SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN __BITS(3,1) 211 #define SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN_MAX __BIT(0) 212 213 #define SUNXI_HDMI_DDC_CTRL_EN __BIT(31) 214 #define SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START __BIT(30) 215 #define SUNXI_HDMI_DDC_CTRL_FIFO_DIR __BIT(8) 216 #define SUNXI_HDMI_DDC_CTRL_FIFO_DIR_READ 0 217 #define SUNXI_HDMI_DDC_CTRL_FIFO_DIR_WRITE 1 218 #define SUNXI_HDMI_DDC_CTRL_SW_RST __BIT(0) 219 220 #define SUNXI_HDMI_DDC_SLAVE_ADDR_0 __BITS(31,24) 221 #define SUNXI_HDMI_DDC_SLAVE_ADDR_1 __BITS(23,16) 222 #define SUNXI_HDMI_DDC_SLAVE_ADDR_2 __BITS(15,8) 223 #define SUNXI_HDMI_DDC_SLAVE_ADDR_3 __BITS(6,0) 224 225 #define SUNXI_HDMI_DDC_INT_STATUS_CLEAR __BIT(8) 226 #define SUNXI_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OP __BIT(7) 227 #define SUNXI_HDMI_DDC_INT_STATUS_RX_UNDERFLOW __BIT(6) 228 #define SUNXI_HDMI_DDC_INT_STATUS_TX_OVERFLOW __BIT(5) 229 #define SUNXI_HDMI_DDC_INT_STATUS_FIFO_REQ __BIT(4) 230 #define SUNXI_HDMI_DDC_INT_STATUS_ARB_ERR __BIT(3) 231 #define SUNXI_HDMI_DDC_INT_STATUS_ACK_ERR __BIT(2) 232 #define SUNXI_HDMI_DDC_INT_STATUS_BUS_ERR __BIT(1) 233 #define SUNXI_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE __BIT(0) 234 235 #define SUNXI_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR __BIT(31) 236 #define SUNXI_HDMI_DDC_FIFO_CTRL_REQUEST_EN __BIT(8) 237 #define SUNXI_HDMI_DDC_FIFO_CTRL_RX_TRIGGER_THRESH __BITS(7,4) 238 #define SUNXI_HDMI_DDC_FIFO_CTRL_TX_TRIGGER_THRESH __BITS(3,0) 239 240 #define SUNXI_HDMI_DDC_FIFO_STATUS_REQ_READY __BIT(7) 241 #define SUNXI_HDMI_DDC_FIFO_STATUS_FULL __BIT(6) 242 #define SUNXI_HDMI_DDC_FIFO_STATUS_EMPTY __BIT(5) 243 #define SUNXI_HDMI_DDC_FIFO_STATUS_LEVEL __BITS(4,0) 244 245 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD __BITS(2,0) 246 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_ABORT 0 247 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_SOREAD 1 248 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOWRITE 2 249 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_IOWRITE 3 250 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD 4 251 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_IOREAD 5 252 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOEDDCREAD 6 253 #define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_IOEDDCREAD 7 254 255 #define SUNXI_HDMI_DDC_CLOCK_M __BITS(6,3) 256 #define SUNXI_HDMI_DDC_CLOCK_N __BITS(2,0) 257 258 #define SUNXI_A31_HDMI_DDC_CTRL_REG 0x0500 259 #define SUNXI_A31_HDMI_DDC_EXCTRL_REG 0x0504 260 #define SUNXI_A31_HDMI_DDC_COMMAND_REG 0x0508 261 #define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG 0x050c 262 #define SUNXI_A31_HDMI_DDC_INT_MASK_REG 0x0510 263 #define SUNXI_A31_HDMI_DDC_INT_STATUS_REG 0x0514 264 #define SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG 0x0518 265 #define SUNXI_A31_HDMI_DDC_FIFO_STATUS_REG 0x051c 266 #define SUNXI_A31_HDMI_DDC_CLOCK_REG 0x0520 267 #define SUNXI_A31_HDMI_DDC_TIMEOUT_REG 0x0524 268 #define SUNXI_A31_HDMI_DDC_FIFO_ACCESS_REG 0x0580 269 270 #define SUNXI_A31_HDMI_DDC_CTRL_SW_RST __BIT(31) 271 #define SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START __BIT(27) 272 #define SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_PULLDOWN __BIT(7) 273 #define SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_EN __BIT(6) 274 #define SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_PULLDOWN __BIT(5) 275 #define SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_EN __BIT(4) 276 #define SUNXI_A31_HDMI_DDC_CTRL_EN __BIT(0) 277 278 #define SUNXI_A31_HDMI_DDC_EXCTRL_BUS_BUSY __BIT(10) 279 #define SUNXI_A31_HDMI_DDC_EXCTRL_SCL_STATUS __BIT(9) 280 #define SUNXI_A31_HDMI_DDC_EXCTRL_SDA_STATUS __BIT(8) 281 #define SUNXI_A31_HDMI_DDC_EXCTRL_SEGMENT_SEL __BIT(7) 282 #define SUNXI_A31_HDMI_DDC_EXCTRL_SEGMENT0_DET __BIT(6) 283 #define SUNXI_A31_HDMI_DDC_EXCTRL_INIT_SEQ_MODE __BIT(5) 284 #define SUNXI_A31_HDMI_DDC_EXCTRL_INIT_SEQ_EN __BIT(4) 285 #define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SCL __BIT(3) 286 #define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SCL_EN __BIT(2) 287 #define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SDA __BIT(1) 288 #define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SDA_EN __BIT(0) 289 290 #define SUNXI_A31_HDMI_DDC_COMMAND_DTC __BITS(25,16) 291 #define SUNXI_A31_HDMI_DDC_COMMAND_CMD __BITS(2,0) 292 293 #define SUNXI_A31_HDMI_DDC_FIFO_CTRL_RST __BIT(15) 294 295 #define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR __BITS(31,24) 296 #define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD __BITS(23,16) 297 #define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR __BITS(15,8) 298 #define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR __BITS(7,1) 299 300