| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterScavenging.cpp | 382 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
422 Register SReg = scavengeVReg(MRI, RS, Reg, true); in scavengeFrameVirtualRegsInBlock() local
448 Register SReg = scavengeVReg(MRI, RS, Reg, false); in scavengeFrameVirtualRegsInBlock() local
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| H A D | LivePhysRegs.cpp | 268 if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) { in addLiveIns()
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| H A D | PrologEpilogInserter.cpp | 1310 for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg)) insertZeroCallUsedRegs() local
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| H A D | BranchFolding.cpp | 860 __anon6bf50fd70302(MCPhysReg SReg) mergeCommonTails() argument
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 153 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 5075 getCorrespondingDRegAndLane(const TargetRegisterInfo * TRI,unsigned SReg,unsigned & Lane) getCorrespondingDRegAndLane() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 128 Register SReg; in optimizeVccBranch() local
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| H A D | SIShrinkInstructions.cpp | 957 Register SReg = Src2->getReg(); runOnMachineFunction() local
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| H A D | SIInstrInfo.cpp | 1240 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect() local
1253 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1267 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1283 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1297 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1309 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1327 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
[all...] |
| H A D | SIISelLowering.cpp | 15350 Register SReg = ST.isWave32() finalizeLowering() local
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| /freebsd-src/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | MemRegion.h | 1035 ParamVarRegion(const Expr * OE,unsigned Idx,const MemRegion * SReg) ParamVarRegion() argument
1312 CXXBaseObjectRegion(const CXXRecordDecl * RD,bool IsVirtual,const SubRegion * SReg) CXXBaseObjectRegion() argument
1350 CXXDerivedObjectRegion(const CXXRecordDecl * DerivedD,const SubRegion * SReg) CXXDerivedObjectRegion() argument
[all...] |
| /freebsd-src/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | MemRegion.cpp | 320 unsigned Idx, const MemRegion *SReg) { in ProfileRegion() argument
422 const MemRegion *SReg) { in ProfileRegion() argument
434 const MemRegion *SReg) { in ProfileRegion() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4931 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4994 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
5056 unsigned SReg = Inst.getOperand(1).getReg(); expandDRotation() local
5119 unsigned SReg = Inst.getOperand(1).getReg(); expandDRotationImm() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1737 Register SRegHi, SReg, VSReg; in eliminateFrameIndex() local
[all...] |
| H A D | PPCISelLowering.cpp | 12174 Register SReg = RegInfo.createVirtualRegister(GPRC); EmitPartwordAtomicBinary() local
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