1 /* $NetBSD: spdreg.h,v 1.4 2014/03/31 11:25:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * spd (PlayStation 2 HDD UNIT) common register define. 34 */ 35 36 /* interrupt */ 37 #define SPD_INTR_ENABLE_REG16 MIPS_PHYS_TO_KSEG1(0x1400002a) 38 #define SPD_INTR_STATUS_REG16 MIPS_PHYS_TO_KSEG1(0x14000028) 39 #define SPD_INTR_CLEAR_REG16 MIPS_PHYS_TO_KSEG1(0x14000128) 40 #define SPD_INTR_EMAC3 0x0040 41 #define SPD_INTR_RXEND 0x0020 42 #define SPD_INTR_TXEND 0x0010 43 #define SPD_INTR_RXDNV 0x0008 44 #define SPD_INTR_TXDNV 0x0004 45 #define SPD_INTR_HDD 0x0001 46 47 /* I/O port */ 48 #define SPD_IO_DIR_REG8 MIPS_PHYS_TO_KSEG1(0x1400002c) 49 #define SPD_IO_DATA_REG8 MIPS_PHYS_TO_KSEG1(0x1400002e) 50 /* HDD LED */ 51 #define SPD_IO_LED 0x0001 52 /* EEPROM (ethernet address) */ 53 #define SPD_IO_OUT 0x0010 54 #define SPD_IO_IN 0x0020 55 #define SPD_IO_CLK 0x0040 56 #define SPD_IO_CS 0x0080 57 58 /* HDD interface */ 59 #define SPD_XFR_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000032) 60 #define SPD_HDD_IO_BASE MIPS_PHYS_TO_KSEG1(0x14000040) 61 #define SPD_IF_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000064) 62 #define SPD_IF_CTRL_ATA_RST 0x80 63 #define SPD_IF_CTRL_DMA_EN 0x04 64 65