| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1238 SDValue &SOffset, SDValue &Offset, in SelectMUBUF()
1323 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64()
1365 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen()
1441 SDValue &SOffset, in SelectMUBUFScratchOffset()
1482 SDValue &SOffset, SDValue &Offset in SelectMUBUFOffset()
1880 SDValue *SOffset, SDValue *Offset, in SelectSMRDOffset()
1967 SDValue *SOffset, SDValue *Offset, in SelectSMRDBaseOffset()
2005 SDValue *SOffset, SDValue *Offset, in SelectSMRD()
2039 SDValue &SOffset, in SelectSMRDSgprImm()
2056 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgprImm(SDValue N, SDValue &SOffset, in SelectSMRDBufferSgprImm()
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| H A D | AMDGPUInstructionSelector.cpp | 3773 Register *SOffset, in selectSmrdOffset()
3872 Register Base, SOffset; in selectSmrdSgpr() local
3882 Register Base, SOffset; in selectSmrdSgprImm() local
4601 MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const { in splitIllegalMUBUFOffset()
4615 Register &SOffset, int64_t &Offset) const { in selectMUBUFAddr64Impl()
4665 MachineOperand &Root, Register &RSrcReg, Register &SOffset, in selectMUBUFOffsetImpl()
4693 Register SOffset; in selectMUBUFAddr64() local
4726 Register SOffset; in selectMUBUFOffset() local
4753 Register SOffset; in selectMUBUFAddr64Atomic() local
4786 Register SOffset; in selectMUBUFOffsetAtomic() local
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| H A D | SIRegisterInfo.cpp | 895 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex() local
1324 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
2481 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); in eliminateFrameIndex() local
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| H A D | AMDGPULegalizerInfo.cpp | 4274 Register VOffset, Register SOffset, in updateBufferMMO()
4418 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
4472 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad()
4529 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
4735 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1258 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1277 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1368 Register SOffset; in applyMappingSBufferLoad() local
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| H A D | SILoadStoreOptimizer.cpp | 97 bool SOffset = false; member
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| H A D | GCNHazardRecognizer.cpp | 829 const MachineOperand *SOffset = in createsVALUHazard() local
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| H A D | SIInstrInfo.cpp | 379 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
6091 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
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| H A D | SIISelLowering.cpp | 7175 SDValue SOffset, SDValue Offset, in updateBufferMMO()
8536 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
8548 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 721 unsigned SOffset = 0; in getMachineOpValue() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 330 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 2566 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4650 StackOffset &SOffset, in isAArch64FrameOffsetLegal()
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