1 /* $NetBSD: pinctrl-zynqmp.h,v 1.1.1.1 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * MIO pin configuration defines for Xilinx ZynqMP 6 * 7 * Copyright (C) 2020 Xilinx, Inc. 8 */ 9 10 #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 12 13 /* Bit value for different voltage levels */ 14 #define IO_STANDARD_LVCMOS33 0 15 #define IO_STANDARD_LVCMOS18 1 16 17 /* Bit values for Slew Rates */ 18 #define SLEW_RATE_FAST 0 19 #define SLEW_RATE_SLOW 1 20 21 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 22