/netbsd-src/external/bsd/pcc/dist/pcc/arch/i86/ |
H A D | table.c | 113 #define SHL SCREG /* shape for long*/ macro
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiAluCode.h | 35 SHL = 0x17, enumerator
|
/netbsd-src/external/bsd/pcc/dist/pcc/cc/cxxcom/ |
H A D | softfloat.c | 156 #define SHL(x,b) ((dword)(x) << b) in soft_div() macro
|
/netbsd-src/external/bsd/pcc/dist/pcc/cc/ccom/ |
H A D | softfloat.c | 156 #define SHL(x,b) ((dword)(x) << b) in soft_div() macro
|
/netbsd-src/usr.bin/xlint/lint1/ |
H A D | op.h | 83 SHL, enumerator
|
/netbsd-src/external/gpl3/binutils.old/dist/gas/config/ |
H A D | rl78-parse.h | 156 SHL = 357, /* SHL */ enumerator 281 #define SHL 357 macro
|
H A D | rl78-parse.c | 342 SHL = 357, /* SHL */ enumerator 467 #define SHL 357 macro
|
/netbsd-src/external/gpl3/binutils/dist/gas/config/ |
H A D | rl78-parse.h | 156 SHL = 357, /* SHL */ enumerator 281 #define SHL 357 macro
|
H A D | rl78-parse.c | 342 SHL = 357, /* SHL */ enumerator 467 #define SHL 357 macro
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 173 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence() local
|
H A D | SystemZISelLowering.cpp | 6532 auto *SHL = CompareLHS->getOperand(0).getNode(); in combineCCMask() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 167 SHL, enumerator
|
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 647 SHL, enumerator
|
/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/ |
H A D | sljitNativeX86_common.c | 233 #define SHL (/* SHIFT */ 4 << 3) macro
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 3893 SDValue SHL = in LowerINTRINSIC_WO_CHAIN() local 12936 SDValue SHL = N->getOperand(0); in PerformSHLSimplify() local 13314 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local 13325 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local 13338 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local 13351 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local 13423 SDValue SHL = OR->getOperand(1); in PerformORCombineToSMULWBT() local 16141 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in PerformShiftCombine() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 2128 WeightedLeaf SHL = Leaves.findSHL(31); in balanceSubTree() local
|
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/TableGen/ |
H A D | Record.h | 808 enum BinaryOp : uint8_t { ADD, SUB, MUL, AND, OR, XOR, SHL, SRA, SRL, LISTCONCAT, enumerator
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 12552 SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1, in lowerShuffleAsBitRotate() local 28090 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R, in LowerScalarImmediateShift() local 28912 SDValue SHL = DAG.getNode(ISD::SHL, DL, VT, R, Amt); in LowerRotate() local
|