xref: /netbsd-src/sys/dev/sdmmc/sdmmc_ioreg.h (revision 45ec1766852ca09d4ebdf96615ea2afb0253092e)
1 /*	$NetBSD: sdmmc_ioreg.h,v 1.6 2019/12/19 17:24:45 kamil Exp $	*/
2 /*	$OpenBSD: sdmmc_ioreg.h,v 1.4 2007/06/02 01:48:37 uwe Exp $	*/
3 
4 /*
5  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef	_SDMMC_IOREG_H_
21 #define	_SDMMC_IOREG_H_
22 
23 /* SDIO commands */				/* response type */
24 #define SD_IO_SEND_OP_COND		5	/* R4 */
25 #define SD_IO_RW_DIRECT			52	/* R5 */
26 #define SD_IO_RW_EXTENDED		53	/* R5? */
27 
28 /* CMD52 arguments */
29 #define SD_ARG_CMD52_READ		(0<<31)
30 #define SD_ARG_CMD52_WRITE		(1UL<<31)
31 #define SD_ARG_CMD52_FUNC_SHIFT		28
32 #define SD_ARG_CMD52_FUNC_MASK		0x7
33 #define SD_ARG_CMD52_EXCHANGE		(1<<27)
34 #define SD_ARG_CMD52_REG_SHIFT		9
35 #define SD_ARG_CMD52_REG_MASK		0x1ffff
36 #define SD_ARG_CMD52_DATA_SHIFT		0
37 #define SD_ARG_CMD52_DATA_MASK		0xff
38 #define SD_R5_DATA(resp)		((resp)[0] & 0xff)
39 
40 /* CMD53 arguments */
41 #define SD_ARG_CMD53_READ		(0<<31)
42 #define SD_ARG_CMD53_WRITE		(1U<<31)
43 #define SD_ARG_CMD53_FUNC_SHIFT		28
44 #define SD_ARG_CMD53_FUNC_MASK		0x7
45 #define SD_ARG_CMD53_BLOCK_MODE		(1<<27)
46 #define SD_ARG_CMD53_INCREMENT		(1<<26)
47 #define SD_ARG_CMD53_REG_SHIFT		9
48 #define SD_ARG_CMD53_REG_MASK		0x1ffff
49 #define SD_ARG_CMD53_LENGTH_SHIFT	0
50 #define SD_ARG_CMD53_LENGTH_MASK	0x1ff
51 #define SD_ARG_CMD53_LENGTH_MAX		64
52 
53 /* 48-bit response decoding (32 bits w/o CRC) */
54 #define MMC_R4(resp)			((resp)[0])
55 #define MMC_R5(resp)			((resp)[0])
56 
57 /* SD R4 response (IO OCR) */
58 #define SD_IO_OCR_MEM_READY		(1U<<31)
59 #define SD_IO_OCR_NUM_FUNCTIONS(ocr)	(((ocr) >> 28) & 0x7)
60 #define SD_IO_OCR_MEM_PRESENT		(1<<27)
61 #define SD_IO_OCR_MASK			0x00fffff0
62 
63 /* Card Common Control Registers (CCCR) */
64 #define SD_IO_CCCR_START		0x00000
65 #define SD_IO_CCCR_SIZE			0x100
66 #define SD_IO_CCCR_CCCR_SDIO_REV	0x00
67 #define SD_IO_CCCR_CCCR_REV(r)		((r) & 0xf)
68 #define  CCCR_CCCR_REV_1_00		0
69 #define  CCCR_CCCR_REV_1_10		1
70 #define  CCCR_CCCR_REV_1_20		2
71 #define  CCCR_CCCR_REV_3_00		3
72 #define SD_IO_CCCR_SDIO_REV(r)		(((r) >> 4) & 0xf)
73 #define  CCCR_SDIO_REV_1_00		0
74 #define  CCCR_SDIO_REV_1_10		1
75 #define  CCCR_SDIO_REV_1_20		2	/* (unreleased) */
76 #define  CCCR_SDIO_REV_2_00		3
77 #define  CCCR_SDIO_REV_3_00		4
78 #define SD_IO_CCCR_SPEC_REV		0x01
79 #define SD_IO_CCCR_SD_PHYS_SPEC_VER(r)	((r) & 0xf)
80 #define  CCCR_SD_PHYS_SPEC_VER_1_01	0
81 #define  CCCR_SD_PHYS_SPEC_VER_1_10	1
82 #define  CCCR_SD_PHYS_SPEC_VER_2_00	2
83 #define  CCCR_SD_PHYS_SPEC_VER_3_00	3
84 #define SD_IO_CCCR_FN_ENABLE		0x02
85 #define SD_IO_CCCR_FN_IOREADY		0x03
86 #define SD_IO_CCCR_FN_INTEN		0x04
87 #define  CCCR_INTEN_INTM		(1<<0)
88 #define SD_IO_CCCR_FN_INTPENDING	0x05
89 #define SD_IO_CCCR_CTL			0x06
90 #define  CCCR_CTL_RES			(1<<3)
91 #define  CCCR_CTL_AS(x)			((x) & 0x7)
92 #define SD_IO_CCCR_BUS_WIDTH		0x07
93 #define  CCCR_BUS_WIDTH_4		(2<<0)
94 #define  CCCR_BUS_WIDTH_1		(0<<0)
95 #define  CCCR_BUS_ECSI			(1<<5)
96 #define  CCCR_BUS_SCSI			(1<<6)
97 #define  CCCR_BUS_NOCD			(1<<7)
98 #define SD_IO_CCCR_CAPABILITY		0x08
99 #define  CCCR_CAPS_SDC			(1<<0)
100 #define  CCCR_CAPS_SMB			(1<<1) /* Multi-Block support */
101 #define  CCCR_CAPS_SRB			(1<<2) /* Read Wait support */
102 #define  CCCR_CAPS_SBS			(1<<3) /* Suspend/Resume support */
103 #define  CCCR_CAPS_S4MI			(1<<4) /* intr support in 4-bit mode */
104 #define  CCCR_CAPS_E4MI			(1<<5) /* enable intr in 4-bit mode */
105 #define  CCCR_CAPS_LSC			(1<<6) /* Low speed card */
106 #define  CCCR_CAPS_4BLS			(1<<7) /* 4-bit support for low speed */
107 #define SD_IO_CCCR_CISPTR		0x09 /* XXX 9-10, 10-11, or 9-12 */
108 #define SD_IO_CCCR_BUS_SUSPEND		0x0c
109 #define SD_IO_CCCR_FUNC_SELECT		0x0d
110 #define SD_IO_CCCR_EXEC_FLAGS		0x0e
111 #define SD_IO_CCCR_READY_FLAGS		0x0f
112 #define  CCCR_FUNC_FS(r)		((r) & 0xf)
113 #define  CCCR_FUNC_FS_FN(fn)		((fn) & 0x7)
114 #define  CCCR_FUNC_FS_MEM		8
115 #define SD_IO_CCCR_FN_EXEC_FLG		0x0e
116 #define SD_IO_CCCR_FN_READY_FLG		0x0f
117 #define SD_IO_CCCR_FN0_BLKSIZ		0x10 /* 0x10-0x11 */
118 #define SD_IO_CCCR_POWER_CTL		0x12
119 #define SD_IO_CCCR_HIGH_SPEED		0x13
120 #define  CCCR_HIGH_SPEED_SHS		(1<<0) /* Support High-Speed */
121 #define  CCCR_HIGH_SPEED_EHS		(1<<1) /* Enable High-Speed */
122 #define  CCCR_HIGH_SPEED_SDR50		(2<<1)
123 #define  CCCR_HIGH_SPEED_SDR104		(3<<1)
124 #define  CCCR_HIGH_SPEED_DDR50		(4<<1)
125 #define SD_IO_CCCR_UHS			0x14
126 #define  CCCR_UHS_SDR50			(1<<0)
127 #define  CCCR_UHS_SDR104		(1<<1)
128 #define  CCCR_UHS_DDR50			(1<<2)
129 #define SD_IO_DRIVE_STRENGTH		0x15
130 #define  CCCR_DRIVE_SDTA		(1<<0)
131 #define  CCCR_DRIVE_SDTC		(1<<1)
132 #define  CCCR_DRIVE_SDTD		(1<<2)
133 
134 /* Function Basic Registers (FBR) */
135 #define SD_IO_FBR_START			0x00100
136 #define SD_IO_FBR_SIZE			0x100
137 #define SD_IO_FBR(func)	((((func) - 1) * SD_IO_FBR_SIZE) + SD_IO_FBR_START)
138 
139 /* FBR offsets */
140 #define SD_IO_FBR_BASIC			0x00
141 #define  FBR_STD_FUNC_IF_CODE(v)	((v) & 0x0f)
142 #define  FBR_STD_FUNC_CSA(v)		((v) & 0x40) /* supports CSA */
143 #define  FBR_STD_FUNC_CSAE(v)		((v) & 0x80) /* enable CSA */
144 #define SD_IO_FBR_EXT			0x01
145 #define SD_IO_FBR_PWR			0x02
146 #define  FBR_PWR_SPS			(1<<0)	/* support power selection */
147 #define  FBR_PWR_EPS			(1<<1)	/* enable low power selection */
148 #define SD_IO_FBR_CIS			0x09	/* 0x109-0x10b */
149 #define SD_IO_FBR_CSA			0x0c	/* 0x10c-0x10e */
150 #define SD_IO_FBR_DATA			0x0f
151 #define SD_IO_FBR_BLOCKLEN		0x10	/* 0x110-0x111 */
152 
153 /* Card Information Structure (CIS) */
154 #define SD_IO_CIS_START			0x01000
155 #define SD_IO_CIS_SIZE			0x17000
156 
157 /* SDIO Standard Function Interface code */
158 #define SD_IO_SFIC_NO_STANDARD		0x0
159 #define SD_IO_SFIC_UART			0x1
160 #define SD_IO_SFIC_TYPEA_BLUETOOTH	0x2	/* Type-A Bluetooth */
161 #define SD_IO_SFIC_TYPEB_BLUETOOTH	0x3	/* Type-B Bluetooth */
162 #define SD_IO_SFIC_GPS			0x4
163 #define SD_IO_SFIC_CAMERA		0x5
164 #define SD_IO_SFIC_PHS			0x6
165 #define SD_IO_SFIC_WLAN			0x7
166 #define SD_IO_SFIC_ATA			0x8	/* Embedded SDIO-ATA */
167 #define SD_IO_SFIC_EXTENDED		0xf	/* See next byte */
168 
169 #endif	/* _SDMMC_IOREG_H_ */
170