/netbsd-src/sys/arch/aarch64/aarch64/ |
H A D | disasm.c | 889 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_b_common() 921 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_h_common() 959 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_w_common() 998 uint64_t Rn, uint64_t Rt, in regoffset_x_common() 1376 OP5FUNC(op_sys, op1, CRn, CRm, op2, Rt) in OP5FUNC() argument 1478 OP3FUNC(op_cbnz, sf, imm19, Rt) in OP3FUNC() argument 1485 OP3FUNC(op_cbz, sf, imm19, Rt) in OP3FUNC() argument 1789 OP3FUNC(op_ldar, size, Rn, Rt) in OP3FUNC() argument 1796 OP2FUNC(op_ldarb, Rn, Rt) in OP2FUNC() argument 1803 OP2FUNC(op_ldarh, Rn, Rt) in OP2FUNC() argument [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local 704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local 749 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local 777 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local 818 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP65GroupBranchMMR6() local 857 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP75GroupBranchMMR6() local 901 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local 946 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local 988 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local 1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local [all …]
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/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
H A D | xray_mips.cc | 42 uint32_t Rt, in encodeInstruction() 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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H A D | xray_mips64.cc | 43 uint32_t Rt, in encodeInstruction() 49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local 385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local 397 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local 594 MCOperand &Rt = Inst.getOperand(1); in HexagonProcessInstruction() local
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H A D | HexagonBitTracker.cpp | 295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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H A D | HexagonSplitDouble.cpp | 375 Register Rt = MI->getOperand(2).getReg(); in profit() local
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H A D | HexagonBitSimplify.cpp | 1895 BitTracker::RegisterRef &Rt) { in matchPackhl() 2028 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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H A D | HexagonISelDAGToDAGHVX.cpp | 2144 SDValue Rt = N->getOperand(2); in selectVAlign() local
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H A D | HexagonInstrInfo.cpp | 1261 Register Rt = Op3.getReg(); in expandPostRAPseudo() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local 1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local 3792 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadShift() local 3876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm8() local 3960 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm12() local 4040 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadT() local 4078 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadLabel() local 4315 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LdStPre() local 4778 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeDoubleRegLoad() local 4801 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore() local [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1075 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local 1136 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local 1334 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local 1417 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local 1551 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeAuthLoadInstruction() local 1830 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 3472 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3479 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3509 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3521 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3544 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3559 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3585 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3595 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3632 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
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H A D | Thumb2SizeReduction.cpp | 467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1391 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local 1812 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local 1832 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local 1855 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 4207 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 4224 unsigned Rt = Inst.getOperand(0).getReg(); in validateInstruction() local 4237 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 4253 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 4286 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 4305 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 4321 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3515 Register Rt = MI.getOperand(1).getReg(); in emitST_F16_PSEUDO() local 3580 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 7415 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction() local 7536 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); in validateLDRDSTRD() local 7761 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local 7774 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local 7821 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
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/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
H A D | CGOpenMPRuntimeGPU.cpp | 1678 auto &Rt = in emitTeamsOutlinedFunction() local
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H A D | CGBuiltin.cpp | 7363 Value *Rt = Builder.CreateTruncOrBitCast(RtAndRt2, Int32Ty); in EmitARMBuiltinExpr() local 7392 Value *Rt = Builder.CreateExtractValue(RtAndRt2, 1); in EmitARMBuiltinExpr() local
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/netbsd-src/external/gpl3/binutils.old/dist/gas/config/ |
H A D | tc-arm.c | 10110 unsigned Rt = inst.operands[0].reg; in do_vmrs() local 10171 unsigned Rt = inst.operands[1].reg; in do_vmsr() local 20055 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; in do_mve_mov() local
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/netbsd-src/external/gpl3/binutils/dist/gas/config/ |
H A D | tc-arm.c | 10140 unsigned Rt = inst.operands[0].reg; in do_vmrs() local 10201 unsigned Rt = inst.operands[1].reg; in do_vmsr() local 20075 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; in do_mve_mov() local
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