| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
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| /netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| H A D | xray_mips.cc | 41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| H A D | xray_mips64.cc | 42 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction()
49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1630 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1650 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1670 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1693 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1726 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1736 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1778 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1795 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1924 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; in isInduction() local
374 Register Rs = MI->getOperand(1).getReg(); in profit() local
476 USet &Rs) { in collectIndRegsForLoop()
580 USet Rs; in collectIndRegs() local
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| H A D | HexagonConstExtenders.cpp | 291 Register Rs; member
445 HCE::Register Rs; member
1503 Register Rs = ExtI.second.Rs; // Only one reg allowed now. in calculatePlacement() local
1800 Register Rs = MI.getOperand(IsSub ? 3 : 2); in replaceInstrExpr() local
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| H A D | HexagonAsmPrinter.cpp | 409 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
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| H A D | HexagonBitTracker.cpp | 295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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| H A D | HexagonBitSimplify.cpp | 1894 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
2028 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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| H A D | HexagonGenInsert.cpp | 1266 void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, in stats()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
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| /netbsd-src/sys/arch/sh3/include/ |
| H A D | locore.h | 209 #define __INTR_MASK_EXCEPTION_UNBLOCK(Rs, Ri, Rb) \ argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ScalarEvolutionDivision.cpp | 149 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
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| /netbsd-src/external/bsd/mdocml/dist/ |
| H A D | mdoc.h | 152 struct mdoc_rs Rs; member
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| /netbsd-src/external/gpl3/gcc.old/dist/libphobos/src/std/algorithm/ |
| H A D | searching.d | 805 foreach (i, Ri; Rs) in foreach()
814 foreach (i, Ri; Rs) in foreach()
823 foreach (i, Ri; Rs) in foreach()
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| /netbsd-src/external/gpl3/gcc/dist/libphobos/src/std/algorithm/ |
| H A D | searching.d | 826 foreach (i, Ri; Rs) in foreach()
835 foreach (i, Ri; Rs) in foreach()
844 foreach (i, Ri; Rs) in foreach()
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| H A D | comparison.d | 1030 private bool equalLoop(Rs...)(ref Rs rs) in equalLoop() argument
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| /netbsd-src/sys/arch/aarch64/aarch64/ |
| H A D | disasm.c | 2838 OP5FUNC(op_stlxp, size, Rs, Rt2, Rn, Rt) argument
2846 OP4FUNC(op_stlxr, size, Rs, Rn, Rt) argument
2853 OP3FUNC(op_stlxrb, Rs, Rn, Rt) argument
2860 OP3FUNC(op_stlxrh, Rs, Rn, Rt) argument
3107 OP5FUNC(op_stxp, size, Rs, Rt2, Rn, Rt) argument
3115 OP4FUNC(op_stxr, size, Rs, Rn, Rt) argument
3123 OP3FUNC(op_stxrb, Rs, Rn, Rt) argument
3131 OP3FUNC(op_stxrh, Rs, Rn, Rt) argument
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/Tooling/Core/ |
| H A D | Replacement.cpp | 221 Replacements Rs(R); in mergeIfOrderIndependent() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1337 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 1518 unsigned Rs = MO1.getReg(); in getSORegRegOpValue() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4320 unsigned Rs = Inst.getOperand(0).getReg(); in validateInstruction() local
4333 unsigned Rs = Inst.getOperand(0).getReg(); in validateInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3527 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO() local
|