| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 578 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
592 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
617 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
647 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
690 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
720 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
761 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
800 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
842 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
887 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
[all …]
|
| /freebsd-src/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_mips.cpp | 40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
|
| H A D | xray_mips64.cpp | 41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
|
| /freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 28 struct Rs { struct
46 Rs rs1; \ argument
|
| H A D | RISCVCInstructions.h | 26 operator Rs() { return Rs{rd + (shift ? 8 : 0)}; } in Rs() function
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1627 MCOperand &Rs = Inst.getOperand(2); processInstruction() local
1647 MCOperand &Rs = Inst.getOperand(2); processInstruction() local
1667 MCOperand &Rs = Inst.getOperand(2); processInstruction() local
1690 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1723 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1733 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1775 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1792 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1921 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; in isInduction() local
373 Register Rs = MI->getOperand(1).getReg(); in profit() local
475 USet &Rs) { in collectIndRegsForLoop() argument
579 USet Rs; collectIndRegs() local
[all...] |
| H A D | HexagonConstExtenders.cpp | 293 Register Rs; member
447 HCE::Register Rs; global() member
1505 Register Rs = ExtI.second.Rs; // Only one reg allowed now. calculatePlacement() local
1802 Register Rs = MI.getOperand(IsSub ? 3 : 2); replaceInstrExpr() local
[all...] |
| H A D | HexagonAsmPrinter.cpp | 410 MCOperand &Rs = Inst.getOperand(1); HexagonProcessInstruction() local
|
| H A D | HexagonBitTracker.cpp | 295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
|
| H A D | HexagonBitSimplify.cpp | 1919 matchPackhl(unsigned SelfR,const BitTracker::RegisterCell & RC,BitTracker::RegisterRef & Rs,BitTracker::RegisterRef & Rt) matchPackhl() argument
2053 BitTracker::RegisterRef Rs, Rt; genPackhl() local
[all...] |
| H A D | HexagonGenInsert.cpp | 1248 void IFOrdering::stats(const RegisterSet &Rs, unsigne argument
[all...] |
| H A D | HexagonFrameLowering.cpp | 2511 Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); expandAlloca() local
[all...] |
| H A D | HexagonInstrInfo.cpp | 1346 Register Rs = Op2.getReg(); expandPostRAPseudo() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolutionDivision.cpp | 151 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 179 Register Rs = TailAdd.getOperand(1).getReg(); foldLargeOffset() local
|
| /freebsd-src/contrib/mandoc/ |
| H A D | mdoc.h | 152 struct mdoc_rs Rs; member
|
| /freebsd-src/contrib/llvm-project/clang/lib/Headers/ |
| H A D | hvx_hexagon_protos.h | 30 #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) argument
4001 #define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,M… argument
4012 #define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs… argument
4023 #define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt… argument
4034 #define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(… argument
4045 #define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,M… argument
4056 #define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs… argument
|
| /freebsd-src/contrib/llvm-project/clang/lib/Tooling/Core/ |
| H A D | Replacement.cpp | 222 Replacements Rs(R); in mergeIfOrderIndependent() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1408 unsigned Rs = fieldFromInstruction(insn, 16, 5); DecodeExclusiveLdStInstruction() local
2050 unsigned Rs = fieldFromInstruction(insn, 16, 5); DecodeCPYMemOpInstruction() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 1540 unsigned Rs = MO1.getReg(); in getSORegRegOpValue() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3514 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); emitST_F16_PSEUDO() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5392 unsigned Rs = Inst.getOperand(0).getReg(); validateInstruction() local
5405 unsigned Rs = Inst.getOperand(0).getReg(); validateInstruction() local
|