Searched defs:RotateAmt (Results 1 – 4 of 4) sorted by relevance
| /llvm-project/llvm/lib/IR/ |
| H A D | Instructions.cpp | 2408 int RotateAmt = -1; matchShuffleAsBitRotate() local
2427 isBitRotateMask(ArrayRef<int> Mask,unsigned EltSizeInBits,unsigned MinSubElts,unsigned MaxSubElts,unsigned & NumSubElts,unsigned & RotateAmt) isBitRotateMask() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5116 SDValue RotateAmt = Val.getOperand(1); in tryAsSingleRLDCL() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4916 isLegalBitRotate(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,MVT & RotateVT,unsigned & RotateAmt) isLegalBitRotate() argument
4942 unsigned RotateAmt; lowerVECTOR_SHUFFLEAsRotate() local
4982 unsigned RotateAmt; lowerShuffleViaVRegSplitting() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 11307 unsigned RotateAmt, NumSubElts; matchShuffleAsBitRotate() local
11330 int RotateAmt = matchShuffleAsBitRotate(RotateVT, VT.getScalarSizeInBits(), lowerShuffleAsBitRotate() local
38069 int RotateAmt = matchShuffleAsBitRotate(ShuffleVT, MaskScalarSizeInBits, matchUnaryPermuteShuffle() local
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