/netbsd-src/sys/arch/aarch64/aarch64/ |
H A D | disasm.c | 799 uint64_t Rn, uint64_t Rd, in extendreg_common() 842 uint64_t Rn, uint64_t Rd, in shiftreg_common() 889 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_b_common() 921 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_h_common() 959 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_w_common() 998 uint64_t Rn, uint64_t Rt, in regoffset_x_common() 1031 uint64_t sf, uint64_t shift, uint64_t imm12, uint64_t Rn, uint64_t Rd, in addsub_imm_common() 1057 uint64_t sf, uint64_t Rm, uint64_t cond, uint64_t Rn, uint64_t Rd, in csetsel_common() 1086 OP4FUNC(op_adc, sf, Rm, Rn, Rd) in OP4FUNC() argument 1094 OP4FUNC(op_adcs, sf, Rm, Rn, Rd) in OP4FUNC() argument [all …]
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H A D | trap.c | 683 int Rn, Rd, Rm, error; in emul_arm_swp() local
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/netbsd-src/sys/arch/sh3/include/ |
H A D | locore.h | 169 #define __EXCEPTION_BLOCK(Rn, Rm) ;\ argument 177 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\ argument 189 #define __INTR_MASK(Rn, Rm) ;\ argument 196 #define __INTR_UNMASK(Rn, Rm) ;\ argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1673 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local 1848 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local 1953 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local 1998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local 2188 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeRFEInstruction() local 2219 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeQADDInstruction() local 2241 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeMemMultipleWritebackInstruction() local 2495 unsigned Rn = fieldFromInstruction(Insn, 0, 4); in DecodeSMLAInstruction() local 2523 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeTSTInstruction() local 2573 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeAddrModeImm12Operand() local [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 890 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local 981 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local 1076 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local 1137 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local 1335 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeExclusiveLdStInstruction() local 1418 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodePairLdStInstruction() local 1552 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAuthLoadInstruction() local 1585 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAddSubERegInstruction() local 1642 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeLogicalImmInstruction() local 1748 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAddSubImmShift() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local 1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue() local 1254 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local 1351 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrMode3OpValue() local 1361 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local 1398 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeISOpValue() local
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/netbsd-src/external/gpl3/binutils.old/dist/gas/config/ |
H A D | tc-arm.c | 9265 unsigned Rn = inst.operands[2].reg; in do_rd_rm_rn() local 9701 unsigned Rd, Rn; in do_co_reg2c() local 9752 unsigned Rd, Rn, Rm; in do_div() local 11603 int Rd, Rn; in do_t_add_sub_w() local 11625 int Rd, Rs, Rn; in do_t_add_sub() local 11892 int Rd, Rs, Rn; in do_t_arit3() local 11980 int Rd, Rs, Rn; in do_t_arit3c() local 12092 int Rd, Rn; in do_t_bfi() local 12122 unsigned Rd, Rn; in do_t_bfx() local 12330 unsigned Rd, Rn, Rm; in do_t_cond() local [all …]
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/netbsd-src/external/gpl3/binutils/dist/gas/config/ |
H A D | tc-arm.c | 9295 unsigned Rn = inst.operands[2].reg; in do_rd_rm_rn() local 9731 unsigned Rd, Rn; in do_co_reg2c() local 9782 unsigned Rd, Rn, Rm; in do_div() local 11633 int Rd, Rn; in do_t_add_sub_w() local 11655 int Rd, Rs, Rn; in do_t_add_sub() local 11922 int Rd, Rs, Rn; in do_t_arit3() local 12010 int Rd, Rs, Rn; in do_t_arit3c() local 12122 int Rd, Rn; in do_t_bfi() local 12152 unsigned Rd, Rn; in do_t_bfx() local 12360 unsigned Rd, Rn, Rm; in do_t_cond() local [all …]
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/netbsd-src/external/gpl3/binutils/dist/include/opcode/ |
H A D | tic30.h | 190 #define Rn 0x0001 macro
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/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/ |
H A D | tic30.h | 190 #define Rn 0x0001 macro
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 4209 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local 4255 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local 4287 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local 4306 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local 4322 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local 4336 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
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H A D | ARMBaseInstrInfo.cpp | 3560 Register Rn = MI.getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local 3586 Register Rn = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local 3596 Register Rn = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local 3633 Register Rn = MI.getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 7571 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateLDRDSTRD() local 7762 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local 7775 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local 7822 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local 7897 unsigned Rn = Inst.getOperand(0).getReg(); in validateInstruction() local 10386 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction() local 10410 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction() local
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/netbsd-src/external/gpl3/binutils/dist/opcodes/ |
H A D | arm-dis.c | 11598 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local 11697 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
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/netbsd-src/external/gpl3/binutils.old/dist/opcodes/ |
H A D | arm-dis.c | 11032 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local 11117 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
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