Searched defs:Rev (Results 1 – 9 of 9) sorted by relevance
| /llvm-project/clang/lib/Basic/Targets/ |
| H A D | SystemZ.cpp | 111 const auto Rev = getISARevision() local
122 for (const ISANameRevision &Rev : ISARevisions) fillValidCPUList() local
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| /llvm-project/clang-tools-extra/clang-tidy/abseil/ |
| H A D | StringFindStartswithCheck.cpp | 95 bool Rev = FindFun->getName().contains("rfind"); in check() local
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| /llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 512 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); in getSingleInstruction() local
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| /llvm-project/clang/utils/TableGen/ |
| H A D | NeonEmitter.cpp | 1590 class Rev : public SetTheory::Operator { emitDagShuffle() class
1594 Rev(unsigned ElementSize) : ElementSize(ElementSize) {} emitDagShuffle() function in Intrinsic::DagEmitter::emitDagShuffle::Rev
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| /llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 1040 unsigned Rev = IsReverseVecRegPair(Producer); in SubregisterBit() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10338 SDValue Rev = DAG.getNode(RevOpcode, dl, VT, Op0); LowerVecReduce() local
16681 __anon6f7513dc1d02(ShuffleVectorSDNode *SVN, bool Rev) PerformSplittingToNarrowingStores() argument
18820 unsigned Rev = VT == MVT::v4i32 ? ARMISD::VREV32 : ARMISD::VREV16; PerformMVEExtCombine() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11340 SDValue Rev = getDataClassTest(Op, ~Mask, Dl, DAG, Subtarget); getDataClassTest() local
11347 SDValue Rev(DAG.getMachineNode( getDataClassTest() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13009 SDValue Rev = DAG.getNode(AArch64ISD::REV64, dl, VT, V1); LowerVECTOR_SHUFFLE() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 53011 SDValue Rev = combineBITREVERSE() local
[all...] |