| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 129 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs, in getFrameHelperName()
272 SmallVectorImpl<unsigned> &Regs, in getOrCreateFrameHelper()
356 SmallVectorImpl<unsigned> &Regs, in shouldUseFrameHelper()
434 SmallVector<unsigned, 8> Regs; in lowerEpilog() local
508 SmallVector<unsigned, 8> Regs; in lowerProlog() local
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| H A D | AArch64ISelDAGToDAG.cpp | 1190 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1199 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1208 SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) { in createZTuple()
1218 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1256 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1494 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1513 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectPredicatedStore() local
1558 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1612 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1651 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 240 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
250 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
259 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
451 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 67 static SDValue createTupleImpl(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createTupleImpl()
85 static SDValue createM1Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createM1Tuple()
95 static SDValue createM2Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createM2Tuple()
104 static SDValue createM4Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createM4Tuple()
110 static SDValue createTuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createTuple()
174 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, in selectVLSEG() local
215 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, in selectVLSEGFF() local
259 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, in selectVLXSEG() local
306 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); in selectVSSEG() local
336 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); in selectVSXSEG() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| H A D | RDFRegisters.h | 153 BitVector Regs; member
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| H A D | RegisterPressure.h | 275 RegSet Regs; variable
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | Taint.cpp | 136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
202 if (const TaintedSubRegions *Regs = in isTainted() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
874 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1441 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1579 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
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| H A D | CodeGenRegisters.cpp | 209 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator()
1121 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1580 CodeGenRegister::Vec Regs; member
1609 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2393 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | RegisterAliasing.cpp | 82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 144 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUPALMetadata.cpp | 162 auto Regs = getRegisters(); in getRegister() local
648 auto Regs = getRegisters(); in toString() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
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| H A D | ARMLoadStoreOptimizer.cpp | 614 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg()
629 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti()
836 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreDouble()
862 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 536 AddressRegs Regs = getRegs(Opc, TII); in setMI() local
1334 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1395 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair() local
1473 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair() local
1628 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferStorePair() local
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| H A D | SIMachineFunctionInfo.cpp | 383 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; in visitSoftInstr() local
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| H A D | AggressiveAntiDepBreaker.cpp | 80 std::vector<unsigned> &Regs, in GetGroupRegs()
554 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
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| H A D | CallingConvLower.cpp | 206 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
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| H A D | RDFRegisters.cpp | 333 BitVector Regs = PRI.getUnitAliases(U); in makeRegRef() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 40 SmallVector<Register, 1> Regs; member in __anond54b29330111::GISelAsmOperandInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 62 SmallVector<Register, 4> Regs; member
|