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Searched defs:RegSeq (Results 1 – 4 of 4) sorted by relevance

/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2244 SDValue RegSeq = createZTuple(Regs); in SelectPostLoadLane() local
1474 SDValue RegSeq = createQTuple(Regs); SelectTable() local
2083 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); SelectStore() local
2102 SDValue RegSeq = createZTuple(Regs); SelectPredicatedStore() local
2147 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); SelectPostStore() local
2206 SDValue RegSeq = createQTuple(Regs); SelectLoadLane() local
2298 SDValue RegSeq = createQTuple(Regs); SelectStoreLane() local
2326 SDValue RegSeq = createQTuple(Regs); SelectPostStoreLane() local
[all...]
/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp190 RegSeqOp RegSeq; member
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5071 auto RegSeq = createQTuple(Regs, MIB); selectShuffleVector() local
6742 Register RegSeq = createQTuple(Regs, MIB); SelectTable() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2380 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); SelectVST() local