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Searched defs:RegClass (Results 1 – 25 of 34) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp33 const MCRegisterClass &RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
H A DRDFRegisters.h143 const TargetRegisterClass *RegClass = nullptr; member
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
H A DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
646 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1885 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1952 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2012 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2126 const TargetRegisterClass *RegClass = in createEntryPHI() local
2264 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2401 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
H A DAMDGPUISelDAGToDAG.cpp371 int RegClass = Desc.operands()[OpIdx].RegClass; in getOperandRegClass() local
446 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1352 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1371 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef() local
1499 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); in tryToFindRegisterToRename() local
H A DAArch64AsmPrinter.cpp873 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp378 SDValue RegClass = in createGPRPairNode() local
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
H A DMachineRegisterInfo.cpp157 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
H A DTargetInstrInfo.cpp52 short RegClass = MCID.operands()[OpNum].RegClass; in getRegClass() local
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1850 SDValue RegClass = in createGPRPairNode() local
1861 SDValue RegClass = in createSRegPairNode() local
1872 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1883 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1895 SDValue RegClass = in createQuadSRegsNode() local
1910 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1925 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
H A DThumb2InstrInfo.cpp544 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
H A DMVETPAndVPTOptimisationsPass.cpp617 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR() local
H A DARMBaseRegisterInfo.cpp855 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
H A DARMFrameLowering.cpp2119 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit() local
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp46 const TargetRegisterClass &RegClass) { in constrainRegToClass()
57 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass()
/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp150 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister()
H A DCodeGenRegisters.cpp1603 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1664 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp934 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
3437 auto &RegClass = in adjustStackWithPops() local
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp590 const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg); in getRegAllocationHints() local
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1904 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp118 #define DECODE_OPERAND_REG(RegClass) \ argument

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