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Searched defs:RegClass (Results 1 – 25 of 33) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp33 const MCRegisterClass &RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
H A DRDFRegisters.h143 const TargetRegisterClass *RegClass = nullptr; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
H A DWebAssemblyRegStackify.cpp106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
639 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp41 const TargetRegisterClass &RegClass) { in constrainRegToClass()
52 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass()
102 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1356 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1375 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef() local
1502 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
H A DAArch64AsmPrinter.cpp756 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
H A DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
H A DLiveIntervals.cpp1741 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in splitSeparateComponents() local
H A DTargetInstrInfo.cpp53 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1912 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1979 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2039 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2154 const TargetRegisterClass *RegClass = in createEntryPHI() local
2292 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2429 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
H A DAMDGPUISelDAGToDAG.cpp577 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
652 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
H A DSIInstrInfo.cpp988 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate() local
3752 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
4458 auto RegClass = TID.OpInfo[OpNum].RegClass; in getRegClass() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp528 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
H A DARMISelDAGToDAG.cpp1831 SDValue RegClass = in createGPRPairNode() local
1842 SDValue RegClass = in createSRegPairNode() local
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1864 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1876 SDValue RegClass = in createQuadSRegsNode() local
1891 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1906 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
H A DMVETPAndVPTOptimisationsPass.cpp579 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR() local
H A DARMBaseRegisterInfo.cpp832 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
H A DARMFrameLowering.cpp1643 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit() local
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp141 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister()
H A DCodeGenRegisters.cpp1544 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1605 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp797 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
3188 auto &RegClass = in adjustStackWithPops() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp112 #define DECODE_OPERAND_REG(RegClass) \ argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1902 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local

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