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Searched defs:RegClass (Results 1 – 25 of 35) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp162 #define DECODE_OPERAND_REG_8(RegClass) \ argument
127 DECODE_OPERAND_REG_8(RegClass) global() argument
150 DECODE_OPERAND_REG_7(RegClass,OpWidth) global() argument
157 DECODE_OPERAND_REG_AV10(RegClass,OpWidth) global() argument
168 DECODE_OPERAND_SRC_REG_A9(RegClass,OpWidth) global() argument
173 DECODE_SRC_OPERAND_REG_AV10(RegClass,OpWidth) global() argument
181 DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass,OpWidth,ImmWidth) global() argument
190 DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass,OpWidth,ImmWidth) global() argument
194 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass,OpWidth,ImmWidth) global() argument
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
H A DRDFRegisters.h183 const TargetRegisterClass *RegClass = nullptr; member
/freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
H A DWebAssemblyRegStackify.cpp104 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); convertImplicitDefToConstZero() local
638 const auto *RegClass = MRI.getRegClass(Reg); moveAndTeeForMultiUse() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1885 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator() local
2012 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs() local
2126 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass); in createEntryPHI() local
1952 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); insertChainedPHI() local
2264 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); createIfRegion() local
2401 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); splitLoopPHI() local
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H A DGCNDPPCombine.cpp196 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; getOperandSize() local
H A DAMDGPUISelDAGToDAG.cpp364 int RegClass = Desc.operands()[OpIdx].RegClass; getOperandRegClass() local
439 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); SelectBuildVector() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
H A DMachineRegisterInfo.cpp157 createVirtualRegister(const TargetRegisterClass * RegClass,StringRef Name) createVirtualRegister() argument
H A DTargetInstrInfo.cpp54 short RegClass = MCID.operands()[OpNum].RegClass; in getRegClass() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp378 SDValue RegClass = createGPRPairNode() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1423 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); canRenameMOP() local
1626 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); tryToFindRegisterToRename() local
1654 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); findRenameRegForSameLdStRegPair() local
H A DAArch64AsmPrinter.cpp991 const TargetRegisterClass *RegClass; PrintAsmOperand() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h309 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp542 const TargetRegisterClass *RegClass = rewriteT2FrameIndex() local
H A DARMISelDAGToDAG.cpp1849 SDValue RegClass = createGPRPairNode() local
1860 SDValue RegClass = createSRegPairNode() local
1871 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, createDRegPairNode() local
1882 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, createQRegPairNode() local
1894 SDValue RegClass = createQuadSRegsNode() local
1909 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, createQuadDRegsNode() local
1924 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, createQuadQRegsNode() local
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H A DMVETPAndVPTOptimisationsPass.cpp617 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR() local
H A DARMBaseRegisterInfo.cpp855 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp151 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
H A DCodeGenRegisters.cpp
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp47 constrainRegToClass(MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const RegisterBankInfo & RBI,Register Reg,const TargetRegisterClass & RegClass) constrainRegToClass() argument
58 constrainOperandRegClass(const MachineFunction & MF,const TargetRegisterInfo & TRI,MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const RegisterBankInfo & RBI,MachineInstr & InsertPt,const TargetRegisterClass & RegClass,MachineOperand & RegMO) constrainOperandRegClass() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp957 CopyReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64() local
3625 auto &RegClass = adjustStackWithPops() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp590 const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg); in getRegAllocationHints() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1982 const TargetRegisterClass *RegClass = constrainOperandRegClass() local

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