| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DynAllocaExpander.cpp | 224 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
238 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
251 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower() local
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| H A D | X86RegisterInfo.cpp | 691 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
669 __anon5236c8c40102(MCRegister RegA, MCRegister RegB) isArgumentRegister() argument
676 __anon5236c8c40202(MCRegister &RegA) isArgumentRegister() argument
686 __anon5236c8c40302(MCRegister &RegA) isArgumentRegister() argument
698 __anon5236c8c40502(MCRegister &RegA) isArgumentRegister() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 473 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const; in isSubRegister() argument
481 isSubRegisterEq(MCRegister RegA,MCRegister RegB) isSubRegisterEq() argument
487 isSuperRegisterEq(MCRegister RegA,MCRegister RegB) isSuperRegisterEq() argument
493 isSuperOrSubRegisterEq(MCRegister RegA,MCRegister RegB) isSuperOrSubRegisterEq() argument
614 isSuperRegister(MCRegister RegA,MCRegister RegB) isSuperRegister() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 471 regsAreCompatible(Register RegA,Register RegB) const regsAreCompatible() argument
560 isProfitableToCommute(Register RegA,Register RegB,Register RegC,MachineInstr * MI,unsigned Dist) isProfitableToCommute() argument
687 Register RegA = MI->getOperand(DstIdx).getReg(); commuteInstruction() local
696 isProfitableToConv3Addr(Register RegA,Register RegB) isProfitableToConv3Addr() argument
715 convertInstTo3Addr(MachineBasicBlock::iterator & mi,MachineBasicBlock::iterator & nmi,Register RegA,Register RegB,unsigned & Dist) convertInstTo3Addr() argument
1496 Register RegA = DstMO.getReg(); processTiedPairs() local
1681 Register RegA = DstMO.getReg(); processStatepoint() local
[all...] |
| H A D | ImplicitNullChecks.cpp | 286 Register RegA = MOA.getReg(); in canReorder() local
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| H A D | TargetInstrInfo.cpp | 1093 Register RegA = OpA.getReg(); reassociateOps() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 135 regsOverlap(MCRegister RegA,MCRegister RegB) const regsOverlap() argument
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 428 regsOverlap(Register RegA,Register RegB) regsOverlap() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2223 for (auto &RegA : DefsA) isDependent() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 510 Register RegA = Prev->getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6887 Register RegA = Root.getOperand(1).getReg(); genSubAdd2SubSub() local
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