| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
220 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
226 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
239 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
246 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII()
|
| H A D | MipsMCCodeEmitter.cpp | 99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 198 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore()
221 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad()
|
| H A D | AArch64FrameLowering.cpp | 760 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
773 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
811 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
822 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
2165 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing()
2195 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing()
2212 unsigned Reg1 = AArch64::NoRegister; member
2508 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
2616 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
|
| H A D | MipsAsmPrinter.cpp | 875 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
895 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
906 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
|
| H A D | MipsSEFrameLowering.cpp | 465 unsigned Reg1 = in emitPrologue() local
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
|
| H A D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in ExpandMI() local
502 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in ExpandMI() local
|
| H A D | X86InstrBuilder.h | 165 unsigned Reg1, bool isKill1, in addRegReg()
|
| H A D | X86AvoidStoreForwardingBlocks.cpp | 396 Register Reg1 = MRI->createVirtualRegister( in buildCopy() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 801 Register Reg1 = Reg; in lowerCRSpilling() local
846 Register Reg1 = Reg; in lowerCRRestore() local
960 Register Reg1 = Reg; in lowerCRBitSpilling() local
|
| H A D | PPCVSXSwapRemoval.cpp | 896 Register Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
748 uint16_t Reg1 = 0; variable
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 1438 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1451 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1506 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1553 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 625 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress()
1101 Register Reg1, Reg2; in parseAddress() local
1465 Register Reg1, Reg2; in parseOperand() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 448 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence()
|
| H A D | Thumb2SizeReduction.cpp | 757 Register Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups()
|
| H A D | RegAllocFast.cpp | 1189 Register Reg1 = MO1.getReg(); in allocateInstruction() local
|
| H A D | TargetInstrInfo.cpp | 185 Register Reg1 = MI.getOperand(Idx1).getReg(); in commuteInstructionImpl() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 100 bool contains(Register Reg1, Register Reg2) const { in contains()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1757 StringRef Reg1(R1); in processInstruction() local
1901 StringRef Reg1(R1); in processInstruction() local
|