| /netbsd-src/sys/arch/aarch64/aarch64/ |
| H A D | disasm.c | 799 uint64_t Rn, uint64_t Rd, in extendreg_common()
842 uint64_t Rn, uint64_t Rd, in shiftreg_common()
1031 uint64_t sf, uint64_t shift, uint64_t imm12, uint64_t Rn, uint64_t Rd, in addsub_imm_common()
1057 uint64_t sf, uint64_t Rm, uint64_t cond, uint64_t Rn, uint64_t Rd, in csetsel_common()
1086 OP4FUNC(op_adc, sf, Rm, Rn, Rd) in OP4FUNC() argument
1094 OP4FUNC(op_adcs, sf, Rm, Rn, Rd) in OP4FUNC() argument
1102 OP6FUNC(op_add_extreg, sf, Rm, option, imm3, Rn, Rd) in OP6FUNC() argument
1108 OP5FUNC(op_add_imm, sf, shift, imm12, Rn, Rd) in OP5FUNC() argument
1129 OP6FUNC(op_add_shiftreg, sf, shift, Rm, imm6, Rn, Rd) in OP6FUNC() argument
1139 OP6FUNC(op_adds_extreg, sf, Rm, option, imm3, Rn, Rd) in OP6FUNC() argument
[all …]
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| H A D | trap.c | 683 int Rn, Rd, Rm, error; in emul_arm_swp() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
362 Register Rd = MI.getOperand(0).getReg(); in apply() local
372 Register Rd = MI.getOperand(0).getReg(); in apply() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 889 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
980 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
1042 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1584 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1641 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1672 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1711 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1728 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1747 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2217 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2443 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2494 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
3037 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
3307 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
3354 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3402 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3437 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| H A D | xray_mips.cc | 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| H A D | xray_mips64.cc | 49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 396 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
406 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
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| /netbsd-src/external/gpl3/binutils.old/dist/gas/config/ |
| H A D | tc-arm.c | 9638 unsigned Rd; in do_co_reg() local
9701 unsigned Rd, Rn; in do_co_reg2c() local
9752 unsigned Rd, Rn, Rm; in do_div() local
11603 int Rd, Rn; in do_t_add_sub_w() local
11625 int Rd, Rs, Rn; in do_t_add_sub() local
11846 unsigned Rd; in do_t_adr() local
11892 int Rd, Rs, Rn; in do_t_arit3() local
11980 int Rd, Rs, Rn; in do_t_arit3c() local
12076 unsigned Rd; in do_t_bfc() local
12092 int Rd, Rn; in do_t_bfi() local
[all …]
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| /netbsd-src/external/gpl3/binutils/dist/gas/config/ |
| H A D | tc-arm.c | 9668 unsigned Rd; in do_co_reg() local
9731 unsigned Rd, Rn; in do_co_reg2c() local
9782 unsigned Rd, Rn, Rm; in do_div() local
11633 int Rd, Rn; in do_t_add_sub_w() local
11655 int Rd, Rs, Rn; in do_t_add_sub() local
11876 unsigned Rd; in do_t_adr() local
11922 int Rd, Rs, Rn; in do_t_arit3() local
12010 int Rd, Rs, Rn; in do_t_arit3c() local
12106 unsigned Rd; in do_t_bfc() local
12122 int Rd, Rn; in do_t_bfi() local
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1692 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1725 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1735 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1923 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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| /netbsd-src/external/gpl3/binutils/dist/include/opcode/ |
| H A D | ft32.h | 290 unsigned int Rd = (op32 >> 20) & 31; in ft32_shortcode() local
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| /netbsd-src/external/gpl3/binutils.old/dist/include/opcode/ |
| H A D | ft32.h | 290 unsigned int Rd = (op32 >> 20) & 31; in ft32_shortcode() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 323 Register Rd; member
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| H A D | HexagonFrameLowering.cpp | 2557 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| H A D | HexagonInstrInfo.cpp | 1258 Register Rd = Op0.getReg(); in expandPostRAPseudo() local
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| /netbsd-src/external/gpl3/binutils/dist/opcodes/ |
| H A D | i386-dis.c | 565 #define Rd { OP_R, d_mode } macro
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