1 /* $NetBSD: sunxi_rsb.h,v 1.1 2017/07/02 18:06:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_SUNXI_RSB_H 30 #define _ARM_SUNXI_RSB_H 31 32 #define RSB_CTRL_REG 0x0000 33 #define RSB_CTRL_START_TRANS __BIT(7) 34 #define RSB_CTRL_ABORT_TRANS __BIT(6) 35 #define RSB_CTRL_GLOBAL_INT_ENB __BIT(1) 36 #define RSB_CTRL_SOFT_RESET __BIT(0) 37 #define RSB_CCR_REG 0x0004 38 #define RSB_CCR_SDA_ODLY __BITS(10,8) 39 #define RSB_CCR_CLK_DIV __BITS(7,0) 40 #define RSB_INTE_REG 0x0008 41 #define RSB_INTE_LOAD_BSY_ENB __BIT(2) 42 #define RSB_INTE_TRANS_ERR_ENB __BIT(1) 43 #define RSB_INTE_TRANS_OVER_ENB __BIT(0) 44 #define RSB_STAT_REG 0x000c 45 #define RSB_STAT_TRANS_ERR_ID __BITS(15,8) 46 #define RSB_STAT_LOAD_BSY __BIT(2) 47 #define RSB_STAT_TRANS_ERR __BIT(1) 48 #define RSB_STAT_TRANS_OVER __BIT(0) 49 #define RSB_STAT_MASK \ 50 (RSB_STAT_LOAD_BSY | \ 51 RSB_STAT_TRANS_ERR | \ 52 RSB_STAT_TRANS_OVER) 53 #define RSB_DADDR0_REG 0x0010 54 #define RSB_DADDR1_REG 0x0014 55 #define RSB_DLEN_REG 0x0018 56 #define RSB_DLEN_READ_WRITE_FLAG __BIT(4) 57 #define RSB_DLEN_ACCESS_LENGTH __BITS(2,0) 58 #define RSB_DATA0_REG 0x001c 59 #define RSB_DATA1_REG 0x0020 60 #define RSB_LCR_REG 0x0024 61 #define RSB_LCR_SCL_STATE __BIT(5) 62 #define RSB_LCR_SDA_STATE __BIT(4) 63 #define RSB_LCR_SCL_CTL __BIT(3) 64 #define RSB_LCR_SCL_CTL_EN __BIT(2) 65 #define RSB_LCR_SDA_CTL __BIT(1) 66 #define RSB_LCR_SDA_CTL_EN __BIT(0) 67 #define RSB_PMCR_REG 0x0028 68 #define RSB_PMCR_PMU_INIT_SEND __BIT(31) 69 #define RSB_PMCR_PMU_INIT_DATA __BITS(23,16) 70 #define RSB_PMCR_PMU_MODE_CTRL_REG_ADDR __BITS(15,8) 71 #define RSB_PMCR_PMU_DEVICE_ADDR __BITS(7,0) 72 #define RSB_CMD_REG 0x002c 73 #define RSB_CMD_IDX __BITS(7,0) 74 #define RSB_CMD_IDX_SRTA 0xe8 75 #define RSB_CMD_IDX_RD8 0x8b 76 #define RSB_CMD_IDX_RD16 0x9c 77 #define RSB_CMD_IDX_RD32 0xa6 78 #define RSB_CMD_IDX_WR8 0x4e 79 #define RSB_CMD_IDX_WR16 0x59 80 #define RSB_CMD_IDX_WR32 0x63 81 #define RSB_DAR_REG 0x0030 82 #define RSB_DAR_RTA __BITS(23,16) 83 #define RSB_DAR_DA __BITS(15,0) 84 85 #endif /* _ARM_SUNXI_RSB_H */ 86