Searched defs:RS1 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project/llvm/unittests/Target/RISCV/ |
| H A D | MCInstrAnalysisTest.cpp | 50 static MCInst jalr(unsigned RD, unsigned RS1 = RISCV::X10) { in jalr()
54 static MCInst cjr(unsigned RS1) { in cjr()
61 static MCInst cjalr(unsigned RS1) { in cjalr()
|
| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 136 EmitBinary(MCStreamer & OutStreamer,unsigned Opcode,MCOperand & RS1,MCOperand & Src2,MCOperand & RD,const MCSubtargetInfo & STI) EmitBinary() argument
148 EmitOR(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI) EmitOR() argument
154 EmitADD(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & RS2,MCOperand & RD,const MCSubtargetInfo & STI) EmitADD() argument
160 EmitSHL(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI) EmitSHL() argument
|
| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 129 emitLEAzii(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI) emitLEAzii() argument
141 emitLEASLrri(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & RS2,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI) emitLEASLrri() argument
153 emitBinary(MCStreamer & OutStreamer,unsigned Opcode,MCOperand & RS1,MCOperand & Src2,MCOperand & RD,const MCSubtargetInfo & STI) emitBinary() argument
164 emitANDrm(MCStreamer & OutStreamer,MCOperand & RS1,MCOperand & Imm,MCOperand & RD,const MCSubtargetInfo & STI) emitANDrm() argument
|
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 917 unsigned RS1 = getRegState(Op1); in splitAslOr() local
|
| /llvm-project/lldb/unittests/Instruction/RISCV/ |
| H A D | TestRISCVEmulator.cpp | 212 using RS1 = uint64_t; typedef
|