xref: /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (revision 82d56013d7b633d116a93943de88e08335357a7c) 
1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "MCTargetDesc/RISCVMatInt.h"
15 #include "RISCV.h"
16 #include "RISCVMachineFunctionInfo.h"
17 #include "RISCVSubtarget.h"
18 #include "RISCVTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Analysis/MemoryLocation.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/MC/MCInstBuilder.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 
30 using namespace llvm;
31 
32 #define GEN_CHECK_COMPRESS_INSTR
33 #include "RISCVGenCompressInstEmitter.inc"
34 
35 #define GET_INSTRINFO_CTOR_DTOR
36 #include "RISCVGenInstrInfo.inc"
37 
38 namespace llvm {
39 namespace RISCVVPseudosTable {
40 
41 using namespace RISCV;
42 
43 #define GET_RISCVVPseudosTable_IMPL
44 #include "RISCVGenSearchableTables.inc"
45 
46 } // namespace RISCVVPseudosTable
47 } // namespace llvm
48 
RISCVInstrInfo(RISCVSubtarget & STI)49 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
50     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
51       STI(STI) {}
52 
getNop() const53 MCInst RISCVInstrInfo::getNop() const {
54   if (STI.getFeatureBits()[RISCV::FeatureStdExtC])
55     return MCInstBuilder(RISCV::C_NOP);
56   return MCInstBuilder(RISCV::ADDI)
57       .addReg(RISCV::X0)
58       .addReg(RISCV::X0)
59       .addImm(0);
60 }
61 
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const62 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
63                                              int &FrameIndex) const {
64   switch (MI.getOpcode()) {
65   default:
66     return 0;
67   case RISCV::LB:
68   case RISCV::LBU:
69   case RISCV::LH:
70   case RISCV::LHU:
71   case RISCV::FLH:
72   case RISCV::LW:
73   case RISCV::FLW:
74   case RISCV::LWU:
75   case RISCV::LD:
76   case RISCV::FLD:
77     break;
78   }
79 
80   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
81       MI.getOperand(2).getImm() == 0) {
82     FrameIndex = MI.getOperand(1).getIndex();
83     return MI.getOperand(0).getReg();
84   }
85 
86   return 0;
87 }
88 
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const89 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
90                                             int &FrameIndex) const {
91   switch (MI.getOpcode()) {
92   default:
93     return 0;
94   case RISCV::SB:
95   case RISCV::SH:
96   case RISCV::SW:
97   case RISCV::FSH:
98   case RISCV::FSW:
99   case RISCV::SD:
100   case RISCV::FSD:
101     break;
102   }
103 
104   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
105       MI.getOperand(2).getImm() == 0) {
106     FrameIndex = MI.getOperand(1).getIndex();
107     return MI.getOperand(0).getReg();
108   }
109 
110   return 0;
111 }
112 
forwardCopyWillClobberTuple(unsigned DstReg,unsigned SrcReg,unsigned NumRegs)113 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
114                                         unsigned NumRegs) {
115   // We really want the positive remainder mod 32 here, that happens to be
116   // easily obtainable with a mask.
117   return ((DstReg - SrcReg) & 0x1f) < NumRegs;
118 }
119 
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,MCRegister DstReg,MCRegister SrcReg,bool KillSrc) const120 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
121                                  MachineBasicBlock::iterator MBBI,
122                                  const DebugLoc &DL, MCRegister DstReg,
123                                  MCRegister SrcReg, bool KillSrc) const {
124   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
125     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
126         .addReg(SrcReg, getKillRegState(KillSrc))
127         .addImm(0);
128     return;
129   }
130 
131   // FPR->FPR copies and VR->VR copies.
132   unsigned Opc;
133   bool IsScalableVector = true;
134   unsigned NF = 1;
135   unsigned LMul = 1;
136   unsigned SubRegIdx = RISCV::sub_vrm1_0;
137   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
138     Opc = RISCV::FSGNJ_H;
139     IsScalableVector = false;
140   } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
141     Opc = RISCV::FSGNJ_S;
142     IsScalableVector = false;
143   } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
144     Opc = RISCV::FSGNJ_D;
145     IsScalableVector = false;
146   } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
147     Opc = RISCV::PseudoVMV1R_V;
148   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
149     Opc = RISCV::PseudoVMV2R_V;
150   } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
151     Opc = RISCV::PseudoVMV4R_V;
152   } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
153     Opc = RISCV::PseudoVMV8R_V;
154   } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
155     Opc = RISCV::PseudoVMV1R_V;
156     SubRegIdx = RISCV::sub_vrm1_0;
157     NF = 2;
158     LMul = 1;
159   } else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
160     Opc = RISCV::PseudoVMV2R_V;
161     SubRegIdx = RISCV::sub_vrm2_0;
162     NF = 2;
163     LMul = 2;
164   } else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
165     Opc = RISCV::PseudoVMV4R_V;
166     SubRegIdx = RISCV::sub_vrm4_0;
167     NF = 2;
168     LMul = 4;
169   } else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
170     Opc = RISCV::PseudoVMV1R_V;
171     SubRegIdx = RISCV::sub_vrm1_0;
172     NF = 3;
173     LMul = 1;
174   } else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
175     Opc = RISCV::PseudoVMV2R_V;
176     SubRegIdx = RISCV::sub_vrm2_0;
177     NF = 3;
178     LMul = 2;
179   } else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
180     Opc = RISCV::PseudoVMV1R_V;
181     SubRegIdx = RISCV::sub_vrm1_0;
182     NF = 4;
183     LMul = 1;
184   } else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
185     Opc = RISCV::PseudoVMV2R_V;
186     SubRegIdx = RISCV::sub_vrm2_0;
187     NF = 4;
188     LMul = 2;
189   } else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
190     Opc = RISCV::PseudoVMV1R_V;
191     SubRegIdx = RISCV::sub_vrm1_0;
192     NF = 5;
193     LMul = 1;
194   } else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
195     Opc = RISCV::PseudoVMV1R_V;
196     SubRegIdx = RISCV::sub_vrm1_0;
197     NF = 6;
198     LMul = 1;
199   } else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
200     Opc = RISCV::PseudoVMV1R_V;
201     SubRegIdx = RISCV::sub_vrm1_0;
202     NF = 7;
203     LMul = 1;
204   } else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
205     Opc = RISCV::PseudoVMV1R_V;
206     SubRegIdx = RISCV::sub_vrm1_0;
207     NF = 8;
208     LMul = 1;
209   } else {
210     llvm_unreachable("Impossible reg-to-reg copy");
211   }
212 
213   if (IsScalableVector) {
214     if (NF == 1) {
215       BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
216           .addReg(SrcReg, getKillRegState(KillSrc));
217     } else {
218       const TargetRegisterInfo *TRI = STI.getRegisterInfo();
219 
220       int I = 0, End = NF, Incr = 1;
221       unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
222       unsigned DstEncoding = TRI->getEncodingValue(DstReg);
223       if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMul)) {
224         I = NF - 1;
225         End = -1;
226         Incr = -1;
227       }
228 
229       for (; I != End; I += Incr) {
230         BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I))
231             .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
232                     getKillRegState(KillSrc));
233       }
234     }
235   } else {
236     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
237         .addReg(SrcReg, getKillRegState(KillSrc))
238         .addReg(SrcReg, getKillRegState(KillSrc));
239   }
240 }
241 
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool IsKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const242 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
243                                          MachineBasicBlock::iterator I,
244                                          Register SrcReg, bool IsKill, int FI,
245                                          const TargetRegisterClass *RC,
246                                          const TargetRegisterInfo *TRI) const {
247   DebugLoc DL;
248   if (I != MBB.end())
249     DL = I->getDebugLoc();
250 
251   MachineFunction *MF = MBB.getParent();
252   MachineFrameInfo &MFI = MF->getFrameInfo();
253 
254   unsigned Opcode;
255   bool IsScalableVector = true;
256   bool IsZvlsseg = true;
257   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
258     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
259              RISCV::SW : RISCV::SD;
260     IsScalableVector = false;
261   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
262     Opcode = RISCV::FSH;
263     IsScalableVector = false;
264   } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
265     Opcode = RISCV::FSW;
266     IsScalableVector = false;
267   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
268     Opcode = RISCV::FSD;
269     IsScalableVector = false;
270   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
271     Opcode = RISCV::PseudoVSPILL_M1;
272     IsZvlsseg = false;
273   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
274     Opcode = RISCV::PseudoVSPILL_M2;
275     IsZvlsseg = false;
276   } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
277     Opcode = RISCV::PseudoVSPILL_M4;
278     IsZvlsseg = false;
279   } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
280     Opcode = RISCV::PseudoVSPILL_M8;
281     IsZvlsseg = false;
282   } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
283     Opcode = RISCV::PseudoVSPILL2_M1;
284   else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
285     Opcode = RISCV::PseudoVSPILL2_M2;
286   else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
287     Opcode = RISCV::PseudoVSPILL2_M4;
288   else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
289     Opcode = RISCV::PseudoVSPILL3_M1;
290   else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
291     Opcode = RISCV::PseudoVSPILL3_M2;
292   else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
293     Opcode = RISCV::PseudoVSPILL4_M1;
294   else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
295     Opcode = RISCV::PseudoVSPILL4_M2;
296   else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
297     Opcode = RISCV::PseudoVSPILL5_M1;
298   else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
299     Opcode = RISCV::PseudoVSPILL6_M1;
300   else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
301     Opcode = RISCV::PseudoVSPILL7_M1;
302   else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
303     Opcode = RISCV::PseudoVSPILL8_M1;
304   else
305     llvm_unreachable("Can't store this register to stack slot");
306 
307   if (IsScalableVector) {
308     MachineMemOperand *MMO = MF->getMachineMemOperand(
309         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
310         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
311 
312     MFI.setStackID(FI, TargetStackID::ScalableVector);
313     auto MIB = BuildMI(MBB, I, DL, get(Opcode))
314                    .addReg(SrcReg, getKillRegState(IsKill))
315                    .addFrameIndex(FI)
316                    .addMemOperand(MMO);
317     if (IsZvlsseg) {
318       // For spilling/reloading Zvlsseg registers, append the dummy field for
319       // the scaled vector length. The argument will be used when expanding
320       // these pseudo instructions.
321       MIB.addReg(RISCV::X0);
322     }
323   } else {
324     MachineMemOperand *MMO = MF->getMachineMemOperand(
325         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
326         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
327 
328     BuildMI(MBB, I, DL, get(Opcode))
329         .addReg(SrcReg, getKillRegState(IsKill))
330         .addFrameIndex(FI)
331         .addImm(0)
332         .addMemOperand(MMO);
333   }
334 }
335 
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DstReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const336 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
337                                           MachineBasicBlock::iterator I,
338                                           Register DstReg, int FI,
339                                           const TargetRegisterClass *RC,
340                                           const TargetRegisterInfo *TRI) const {
341   DebugLoc DL;
342   if (I != MBB.end())
343     DL = I->getDebugLoc();
344 
345   MachineFunction *MF = MBB.getParent();
346   MachineFrameInfo &MFI = MF->getFrameInfo();
347 
348   unsigned Opcode;
349   bool IsScalableVector = true;
350   bool IsZvlsseg = true;
351   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
352     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
353              RISCV::LW : RISCV::LD;
354     IsScalableVector = false;
355   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
356     Opcode = RISCV::FLH;
357     IsScalableVector = false;
358   } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
359     Opcode = RISCV::FLW;
360     IsScalableVector = false;
361   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
362     Opcode = RISCV::FLD;
363     IsScalableVector = false;
364   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
365     Opcode = RISCV::PseudoVRELOAD_M1;
366     IsZvlsseg = false;
367   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
368     Opcode = RISCV::PseudoVRELOAD_M2;
369     IsZvlsseg = false;
370   } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
371     Opcode = RISCV::PseudoVRELOAD_M4;
372     IsZvlsseg = false;
373   } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
374     Opcode = RISCV::PseudoVRELOAD_M8;
375     IsZvlsseg = false;
376   } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
377     Opcode = RISCV::PseudoVRELOAD2_M1;
378   else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
379     Opcode = RISCV::PseudoVRELOAD2_M2;
380   else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
381     Opcode = RISCV::PseudoVRELOAD2_M4;
382   else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
383     Opcode = RISCV::PseudoVRELOAD3_M1;
384   else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
385     Opcode = RISCV::PseudoVRELOAD3_M2;
386   else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
387     Opcode = RISCV::PseudoVRELOAD4_M1;
388   else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
389     Opcode = RISCV::PseudoVRELOAD4_M2;
390   else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
391     Opcode = RISCV::PseudoVRELOAD5_M1;
392   else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
393     Opcode = RISCV::PseudoVRELOAD6_M1;
394   else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
395     Opcode = RISCV::PseudoVRELOAD7_M1;
396   else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
397     Opcode = RISCV::PseudoVRELOAD8_M1;
398   else
399     llvm_unreachable("Can't load this register from stack slot");
400 
401   if (IsScalableVector) {
402     MachineMemOperand *MMO = MF->getMachineMemOperand(
403         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
404         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
405 
406     MFI.setStackID(FI, TargetStackID::ScalableVector);
407     auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg)
408                    .addFrameIndex(FI)
409                    .addMemOperand(MMO);
410     if (IsZvlsseg) {
411       // For spilling/reloading Zvlsseg registers, append the dummy field for
412       // the scaled vector length. The argument will be used when expanding
413       // these pseudo instructions.
414       MIB.addReg(RISCV::X0);
415     }
416   } else {
417     MachineMemOperand *MMO = MF->getMachineMemOperand(
418         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
419         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
420 
421     BuildMI(MBB, I, DL, get(Opcode), DstReg)
422         .addFrameIndex(FI)
423         .addImm(0)
424         .addMemOperand(MMO);
425   }
426 }
427 
movImm(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,Register DstReg,uint64_t Val,MachineInstr::MIFlag Flag) const428 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
429                             MachineBasicBlock::iterator MBBI,
430                             const DebugLoc &DL, Register DstReg, uint64_t Val,
431                             MachineInstr::MIFlag Flag) const {
432   MachineFunction *MF = MBB.getParent();
433   MachineRegisterInfo &MRI = MF->getRegInfo();
434   bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
435   Register SrcReg = RISCV::X0;
436   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
437   unsigned Num = 0;
438 
439   if (!IsRV64 && !isInt<32>(Val))
440     report_fatal_error("Should only materialize 32-bit constants for RV32");
441 
442   RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, IsRV64);
443   assert(Seq.size() > 0);
444 
445   for (RISCVMatInt::Inst &Inst : Seq) {
446     // Write the final result to DstReg if it's the last instruction in the Seq.
447     // Otherwise, write the result to the temp register.
448     if (++Num == Seq.size())
449       Result = DstReg;
450 
451     if (Inst.Opc == RISCV::LUI) {
452       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
453           .addImm(Inst.Imm)
454           .setMIFlag(Flag);
455     } else {
456       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
457           .addReg(SrcReg, RegState::Kill)
458           .addImm(Inst.Imm)
459           .setMIFlag(Flag);
460     }
461     // Only the first instruction has X0 as its source.
462     SrcReg = Result;
463   }
464 }
465 
466 // The contents of values added to Cond are not examined outside of
467 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
468 // push BranchOpcode, Reg1, Reg2.
parseCondBranch(MachineInstr & LastInst,MachineBasicBlock * & Target,SmallVectorImpl<MachineOperand> & Cond)469 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
470                             SmallVectorImpl<MachineOperand> &Cond) {
471   // Block ends with fall-through condbranch.
472   assert(LastInst.getDesc().isConditionalBranch() &&
473          "Unknown conditional branch");
474   Target = LastInst.getOperand(2).getMBB();
475   Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
476   Cond.push_back(LastInst.getOperand(0));
477   Cond.push_back(LastInst.getOperand(1));
478 }
479 
getOppositeBranchOpcode(int Opc)480 static unsigned getOppositeBranchOpcode(int Opc) {
481   switch (Opc) {
482   default:
483     llvm_unreachable("Unrecognized conditional branch");
484   case RISCV::BEQ:
485     return RISCV::BNE;
486   case RISCV::BNE:
487     return RISCV::BEQ;
488   case RISCV::BLT:
489     return RISCV::BGE;
490   case RISCV::BGE:
491     return RISCV::BLT;
492   case RISCV::BLTU:
493     return RISCV::BGEU;
494   case RISCV::BGEU:
495     return RISCV::BLTU;
496   }
497 }
498 
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const499 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
500                                    MachineBasicBlock *&TBB,
501                                    MachineBasicBlock *&FBB,
502                                    SmallVectorImpl<MachineOperand> &Cond,
503                                    bool AllowModify) const {
504   TBB = FBB = nullptr;
505   Cond.clear();
506 
507   // If the block has no terminators, it just falls into the block after it.
508   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
509   if (I == MBB.end() || !isUnpredicatedTerminator(*I))
510     return false;
511 
512   // Count the number of terminators and find the first unconditional or
513   // indirect branch.
514   MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
515   int NumTerminators = 0;
516   for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
517        J++) {
518     NumTerminators++;
519     if (J->getDesc().isUnconditionalBranch() ||
520         J->getDesc().isIndirectBranch()) {
521       FirstUncondOrIndirectBr = J.getReverse();
522     }
523   }
524 
525   // If AllowModify is true, we can erase any terminators after
526   // FirstUncondOrIndirectBR.
527   if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
528     while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
529       std::next(FirstUncondOrIndirectBr)->eraseFromParent();
530       NumTerminators--;
531     }
532     I = FirstUncondOrIndirectBr;
533   }
534 
535   // We can't handle blocks that end in an indirect branch.
536   if (I->getDesc().isIndirectBranch())
537     return true;
538 
539   // We can't handle blocks with more than 2 terminators.
540   if (NumTerminators > 2)
541     return true;
542 
543   // Handle a single unconditional branch.
544   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
545     TBB = getBranchDestBlock(*I);
546     return false;
547   }
548 
549   // Handle a single conditional branch.
550   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
551     parseCondBranch(*I, TBB, Cond);
552     return false;
553   }
554 
555   // Handle a conditional branch followed by an unconditional branch.
556   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
557       I->getDesc().isUnconditionalBranch()) {
558     parseCondBranch(*std::prev(I), TBB, Cond);
559     FBB = getBranchDestBlock(*I);
560     return false;
561   }
562 
563   // Otherwise, we can't handle this.
564   return true;
565 }
566 
removeBranch(MachineBasicBlock & MBB,int * BytesRemoved) const567 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
568                                       int *BytesRemoved) const {
569   if (BytesRemoved)
570     *BytesRemoved = 0;
571   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
572   if (I == MBB.end())
573     return 0;
574 
575   if (!I->getDesc().isUnconditionalBranch() &&
576       !I->getDesc().isConditionalBranch())
577     return 0;
578 
579   // Remove the branch.
580   if (BytesRemoved)
581     *BytesRemoved += getInstSizeInBytes(*I);
582   I->eraseFromParent();
583 
584   I = MBB.end();
585 
586   if (I == MBB.begin())
587     return 1;
588   --I;
589   if (!I->getDesc().isConditionalBranch())
590     return 1;
591 
592   // Remove the branch.
593   if (BytesRemoved)
594     *BytesRemoved += getInstSizeInBytes(*I);
595   I->eraseFromParent();
596   return 2;
597 }
598 
599 // Inserts a branch into the end of the specific MachineBasicBlock, returning
600 // the number of instructions inserted.
insertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL,int * BytesAdded) const601 unsigned RISCVInstrInfo::insertBranch(
602     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
603     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
604   if (BytesAdded)
605     *BytesAdded = 0;
606 
607   // Shouldn't be a fall through.
608   assert(TBB && "insertBranch must not be told to insert a fallthrough");
609   assert((Cond.size() == 3 || Cond.size() == 0) &&
610          "RISCV branch conditions have two components!");
611 
612   // Unconditional branch.
613   if (Cond.empty()) {
614     MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
615     if (BytesAdded)
616       *BytesAdded += getInstSizeInBytes(MI);
617     return 1;
618   }
619 
620   // Either a one or two-way conditional branch.
621   unsigned Opc = Cond[0].getImm();
622   MachineInstr &CondMI =
623       *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
624   if (BytesAdded)
625     *BytesAdded += getInstSizeInBytes(CondMI);
626 
627   // One-way conditional branch.
628   if (!FBB)
629     return 1;
630 
631   // Two-way conditional branch.
632   MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
633   if (BytesAdded)
634     *BytesAdded += getInstSizeInBytes(MI);
635   return 2;
636 }
637 
insertIndirectBranch(MachineBasicBlock & MBB,MachineBasicBlock & DestBB,const DebugLoc & DL,int64_t BrOffset,RegScavenger * RS) const638 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
639                                               MachineBasicBlock &DestBB,
640                                               const DebugLoc &DL,
641                                               int64_t BrOffset,
642                                               RegScavenger *RS) const {
643   assert(RS && "RegScavenger required for long branching");
644   assert(MBB.empty() &&
645          "new block should be inserted for expanding unconditional branch");
646   assert(MBB.pred_size() == 1);
647 
648   MachineFunction *MF = MBB.getParent();
649   MachineRegisterInfo &MRI = MF->getRegInfo();
650 
651   if (!isInt<32>(BrOffset))
652     report_fatal_error(
653         "Branch offsets outside of the signed 32-bit range not supported");
654 
655   // FIXME: A virtual register must be used initially, as the register
656   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
657   // uses the same workaround).
658   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
659   auto II = MBB.end();
660 
661   MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
662                           .addReg(ScratchReg, RegState::Define | RegState::Dead)
663                           .addMBB(&DestBB, RISCVII::MO_CALL);
664 
665   RS->enterBasicBlockEnd(MBB);
666   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
667                                                 MI.getIterator(), false, 0);
668   MRI.replaceRegWith(ScratchReg, Scav);
669   MRI.clearVirtRegs();
670   RS->setRegUsed(Scav);
671   return 8;
672 }
673 
reverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const674 bool RISCVInstrInfo::reverseBranchCondition(
675     SmallVectorImpl<MachineOperand> &Cond) const {
676   assert((Cond.size() == 3) && "Invalid branch condition!");
677   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
678   return false;
679 }
680 
681 MachineBasicBlock *
getBranchDestBlock(const MachineInstr & MI) const682 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
683   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
684   // The branch target is always the last operand.
685   int NumOp = MI.getNumExplicitOperands();
686   return MI.getOperand(NumOp - 1).getMBB();
687 }
688 
isBranchOffsetInRange(unsigned BranchOp,int64_t BrOffset) const689 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
690                                            int64_t BrOffset) const {
691   unsigned XLen = STI.getXLen();
692   // Ideally we could determine the supported branch offset from the
693   // RISCVII::FormMask, but this can't be used for Pseudo instructions like
694   // PseudoBR.
695   switch (BranchOp) {
696   default:
697     llvm_unreachable("Unexpected opcode!");
698   case RISCV::BEQ:
699   case RISCV::BNE:
700   case RISCV::BLT:
701   case RISCV::BGE:
702   case RISCV::BLTU:
703   case RISCV::BGEU:
704     return isIntN(13, BrOffset);
705   case RISCV::JAL:
706   case RISCV::PseudoBR:
707     return isIntN(21, BrOffset);
708   case RISCV::PseudoJump:
709     return isIntN(32, SignExtend64(BrOffset + 0x800, XLen));
710   }
711 }
712 
getInstSizeInBytes(const MachineInstr & MI) const713 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
714   unsigned Opcode = MI.getOpcode();
715 
716   switch (Opcode) {
717   default: {
718     if (MI.getParent() && MI.getParent()->getParent()) {
719       const auto MF = MI.getMF();
720       const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
721       const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
722       const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
723       const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
724       if (isCompressibleInst(MI, &ST, MRI, STI))
725         return 2;
726     }
727     return get(Opcode).getSize();
728   }
729   case TargetOpcode::EH_LABEL:
730   case TargetOpcode::IMPLICIT_DEF:
731   case TargetOpcode::KILL:
732   case TargetOpcode::DBG_VALUE:
733     return 0;
734   // These values are determined based on RISCVExpandAtomicPseudoInsts,
735   // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
736   // pseudos are expanded.
737   case RISCV::PseudoCALLReg:
738   case RISCV::PseudoCALL:
739   case RISCV::PseudoJump:
740   case RISCV::PseudoTAIL:
741   case RISCV::PseudoLLA:
742   case RISCV::PseudoLA:
743   case RISCV::PseudoLA_TLS_IE:
744   case RISCV::PseudoLA_TLS_GD:
745     return 8;
746   case RISCV::PseudoAtomicLoadNand32:
747   case RISCV::PseudoAtomicLoadNand64:
748     return 20;
749   case RISCV::PseudoMaskedAtomicSwap32:
750   case RISCV::PseudoMaskedAtomicLoadAdd32:
751   case RISCV::PseudoMaskedAtomicLoadSub32:
752     return 28;
753   case RISCV::PseudoMaskedAtomicLoadNand32:
754     return 32;
755   case RISCV::PseudoMaskedAtomicLoadMax32:
756   case RISCV::PseudoMaskedAtomicLoadMin32:
757     return 44;
758   case RISCV::PseudoMaskedAtomicLoadUMax32:
759   case RISCV::PseudoMaskedAtomicLoadUMin32:
760     return 36;
761   case RISCV::PseudoCmpXchg32:
762   case RISCV::PseudoCmpXchg64:
763     return 16;
764   case RISCV::PseudoMaskedCmpXchg32:
765     return 32;
766   case TargetOpcode::INLINEASM:
767   case TargetOpcode::INLINEASM_BR: {
768     const MachineFunction &MF = *MI.getParent()->getParent();
769     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
770     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
771                               *TM.getMCAsmInfo());
772   }
773   case RISCV::PseudoVSPILL2_M1:
774   case RISCV::PseudoVSPILL2_M2:
775   case RISCV::PseudoVSPILL2_M4:
776   case RISCV::PseudoVSPILL3_M1:
777   case RISCV::PseudoVSPILL3_M2:
778   case RISCV::PseudoVSPILL4_M1:
779   case RISCV::PseudoVSPILL4_M2:
780   case RISCV::PseudoVSPILL5_M1:
781   case RISCV::PseudoVSPILL6_M1:
782   case RISCV::PseudoVSPILL7_M1:
783   case RISCV::PseudoVSPILL8_M1:
784   case RISCV::PseudoVRELOAD2_M1:
785   case RISCV::PseudoVRELOAD2_M2:
786   case RISCV::PseudoVRELOAD2_M4:
787   case RISCV::PseudoVRELOAD3_M1:
788   case RISCV::PseudoVRELOAD3_M2:
789   case RISCV::PseudoVRELOAD4_M1:
790   case RISCV::PseudoVRELOAD4_M2:
791   case RISCV::PseudoVRELOAD5_M1:
792   case RISCV::PseudoVRELOAD6_M1:
793   case RISCV::PseudoVRELOAD7_M1:
794   case RISCV::PseudoVRELOAD8_M1: {
795     // The values are determined based on expandVSPILL and expandVRELOAD that
796     // expand the pseudos depending on NF.
797     unsigned NF = isRVVSpillForZvlsseg(Opcode)->first;
798     return 4 * (2 * NF - 1);
799   }
800   }
801 }
802 
isAsCheapAsAMove(const MachineInstr & MI) const803 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
804   const unsigned Opcode = MI.getOpcode();
805   switch (Opcode) {
806   default:
807     break;
808   case RISCV::FSGNJ_D:
809   case RISCV::FSGNJ_S:
810     // The canonical floating-point move is fsgnj rd, rs, rs.
811     return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
812            MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
813   case RISCV::ADDI:
814   case RISCV::ORI:
815   case RISCV::XORI:
816     return (MI.getOperand(1).isReg() &&
817             MI.getOperand(1).getReg() == RISCV::X0) ||
818            (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
819   }
820   return MI.isAsCheapAsAMove();
821 }
822 
823 Optional<DestSourcePair>
isCopyInstrImpl(const MachineInstr & MI) const824 RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
825   if (MI.isMoveReg())
826     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
827   switch (MI.getOpcode()) {
828   default:
829     break;
830   case RISCV::ADDI:
831     // Operand 1 can be a frameindex but callers expect registers
832     if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
833         MI.getOperand(2).getImm() == 0)
834       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
835     break;
836   case RISCV::FSGNJ_D:
837   case RISCV::FSGNJ_S:
838     // The canonical floating-point move is fsgnj rd, rs, rs.
839     if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
840         MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
841       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
842     break;
843   }
844   return None;
845 }
846 
verifyInstruction(const MachineInstr & MI,StringRef & ErrInfo) const847 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
848                                        StringRef &ErrInfo) const {
849   const MCInstrInfo *MCII = STI.getInstrInfo();
850   MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
851 
852   for (auto &OI : enumerate(Desc.operands())) {
853     unsigned OpType = OI.value().OperandType;
854     if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
855         OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
856       const MachineOperand &MO = MI.getOperand(OI.index());
857       if (MO.isImm()) {
858         int64_t Imm = MO.getImm();
859         bool Ok;
860         switch (OpType) {
861         default:
862           llvm_unreachable("Unexpected operand type");
863         case RISCVOp::OPERAND_UIMM4:
864           Ok = isUInt<4>(Imm);
865           break;
866         case RISCVOp::OPERAND_UIMM5:
867           Ok = isUInt<5>(Imm);
868           break;
869         case RISCVOp::OPERAND_UIMM12:
870           Ok = isUInt<12>(Imm);
871           break;
872         case RISCVOp::OPERAND_SIMM12:
873           Ok = isInt<12>(Imm);
874           break;
875         case RISCVOp::OPERAND_UIMM20:
876           Ok = isUInt<20>(Imm);
877           break;
878         case RISCVOp::OPERAND_UIMMLOG2XLEN:
879           if (STI.getTargetTriple().isArch64Bit())
880             Ok = isUInt<6>(Imm);
881           else
882             Ok = isUInt<5>(Imm);
883           break;
884         }
885         if (!Ok) {
886           ErrInfo = "Invalid immediate";
887           return false;
888         }
889       }
890     }
891   }
892 
893   return true;
894 }
895 
896 // Return true if get the base operand, byte offset of an instruction and the
897 // memory width. Width is the size of memory that is being loaded/stored.
getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseReg,int64_t & Offset,unsigned & Width,const TargetRegisterInfo * TRI) const898 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
899     const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
900     unsigned &Width, const TargetRegisterInfo *TRI) const {
901   if (!LdSt.mayLoadOrStore())
902     return false;
903 
904   // Here we assume the standard RISC-V ISA, which uses a base+offset
905   // addressing mode. You'll need to relax these conditions to support custom
906   // load/stores instructions.
907   if (LdSt.getNumExplicitOperands() != 3)
908     return false;
909   if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
910     return false;
911 
912   if (!LdSt.hasOneMemOperand())
913     return false;
914 
915   Width = (*LdSt.memoperands_begin())->getSize();
916   BaseReg = &LdSt.getOperand(1);
917   Offset = LdSt.getOperand(2).getImm();
918   return true;
919 }
920 
areMemAccessesTriviallyDisjoint(const MachineInstr & MIa,const MachineInstr & MIb) const921 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
922     const MachineInstr &MIa, const MachineInstr &MIb) const {
923   assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
924   assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
925 
926   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
927       MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
928     return false;
929 
930   // Retrieve the base register, offset from the base register and width. Width
931   // is the size of memory that is being loaded/stored (e.g. 1, 2, 4).  If
932   // base registers are identical, and the offset of a lower memory access +
933   // the width doesn't overlap the offset of a higher memory access,
934   // then the memory accesses are different.
935   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
936   const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
937   int64_t OffsetA = 0, OffsetB = 0;
938   unsigned int WidthA = 0, WidthB = 0;
939   if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
940       getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
941     if (BaseOpA->isIdenticalTo(*BaseOpB)) {
942       int LowOffset = std::min(OffsetA, OffsetB);
943       int HighOffset = std::max(OffsetA, OffsetB);
944       int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
945       if (LowOffset + LowWidth <= HighOffset)
946         return true;
947     }
948   }
949   return false;
950 }
951 
952 std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const953 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
954   const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
955   return std::make_pair(TF & Mask, TF & ~Mask);
956 }
957 
958 ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const959 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
960   using namespace RISCVII;
961   static const std::pair<unsigned, const char *> TargetFlags[] = {
962       {MO_CALL, "riscv-call"},
963       {MO_PLT, "riscv-plt"},
964       {MO_LO, "riscv-lo"},
965       {MO_HI, "riscv-hi"},
966       {MO_PCREL_LO, "riscv-pcrel-lo"},
967       {MO_PCREL_HI, "riscv-pcrel-hi"},
968       {MO_GOT_HI, "riscv-got-hi"},
969       {MO_TPREL_LO, "riscv-tprel-lo"},
970       {MO_TPREL_HI, "riscv-tprel-hi"},
971       {MO_TPREL_ADD, "riscv-tprel-add"},
972       {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
973       {MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
974   return makeArrayRef(TargetFlags);
975 }
isFunctionSafeToOutlineFrom(MachineFunction & MF,bool OutlineFromLinkOnceODRs) const976 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
977     MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
978   const Function &F = MF.getFunction();
979 
980   // Can F be deduplicated by the linker? If it can, don't outline from it.
981   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
982     return false;
983 
984   // Don't outline from functions with section markings; the program could
985   // expect that all the code is in the named section.
986   if (F.hasSection())
987     return false;
988 
989   // It's safe to outline from MF.
990   return true;
991 }
992 
isMBBSafeToOutlineFrom(MachineBasicBlock & MBB,unsigned & Flags) const993 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
994                                             unsigned &Flags) const {
995   // More accurate safety checking is done in getOutliningCandidateInfo.
996   return true;
997 }
998 
999 // Enum values indicating how an outlined call should be constructed.
1000 enum MachineOutlinerConstructionID {
1001   MachineOutlinerDefault
1002 };
1003 
getOutliningCandidateInfo(std::vector<outliner::Candidate> & RepeatedSequenceLocs) const1004 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
1005     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1006 
1007   // First we need to filter out candidates where the X5 register (IE t0) can't
1008   // be used to setup the function call.
1009   auto CannotInsertCall = [](outliner::Candidate &C) {
1010     const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
1011 
1012     C.initLRU(*TRI);
1013     LiveRegUnits LRU = C.LRU;
1014     return !LRU.available(RISCV::X5);
1015   };
1016 
1017   llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
1018 
1019   // If the sequence doesn't have enough candidates left, then we're done.
1020   if (RepeatedSequenceLocs.size() < 2)
1021     return outliner::OutlinedFunction();
1022 
1023   unsigned SequenceSize = 0;
1024 
1025   auto I = RepeatedSequenceLocs[0].front();
1026   auto E = std::next(RepeatedSequenceLocs[0].back());
1027   for (; I != E; ++I)
1028     SequenceSize += getInstSizeInBytes(*I);
1029 
1030   // call t0, function = 8 bytes.
1031   unsigned CallOverhead = 8;
1032   for (auto &C : RepeatedSequenceLocs)
1033     C.setCallInfo(MachineOutlinerDefault, CallOverhead);
1034 
1035   // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
1036   unsigned FrameOverhead = 4;
1037   if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
1038           .getFeatureBits()[RISCV::FeatureStdExtC])
1039     FrameOverhead = 2;
1040 
1041   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
1042                                     FrameOverhead, MachineOutlinerDefault);
1043 }
1044 
1045 outliner::InstrType
getOutliningType(MachineBasicBlock::iterator & MBBI,unsigned Flags) const1046 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
1047                                  unsigned Flags) const {
1048   MachineInstr &MI = *MBBI;
1049   MachineBasicBlock *MBB = MI.getParent();
1050   const TargetRegisterInfo *TRI =
1051       MBB->getParent()->getSubtarget().getRegisterInfo();
1052 
1053   // Positions generally can't safely be outlined.
1054   if (MI.isPosition()) {
1055     // We can manually strip out CFI instructions later.
1056     if (MI.isCFIInstruction())
1057       return outliner::InstrType::Invisible;
1058 
1059     return outliner::InstrType::Illegal;
1060   }
1061 
1062   // Don't trust the user to write safe inline assembly.
1063   if (MI.isInlineAsm())
1064     return outliner::InstrType::Illegal;
1065 
1066   // We can't outline branches to other basic blocks.
1067   if (MI.isTerminator() && !MBB->succ_empty())
1068     return outliner::InstrType::Illegal;
1069 
1070   // We need support for tail calls to outlined functions before return
1071   // statements can be allowed.
1072   if (MI.isReturn())
1073     return outliner::InstrType::Illegal;
1074 
1075   // Don't allow modifying the X5 register which we use for return addresses for
1076   // these outlined functions.
1077   if (MI.modifiesRegister(RISCV::X5, TRI) ||
1078       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
1079     return outliner::InstrType::Illegal;
1080 
1081   // Make sure the operands don't reference something unsafe.
1082   for (const auto &MO : MI.operands())
1083     if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI())
1084       return outliner::InstrType::Illegal;
1085 
1086   // Don't allow instructions which won't be materialized to impact outlining
1087   // analysis.
1088   if (MI.isMetaInstruction())
1089     return outliner::InstrType::Invisible;
1090 
1091   return outliner::InstrType::Legal;
1092 }
1093 
buildOutlinedFrame(MachineBasicBlock & MBB,MachineFunction & MF,const outliner::OutlinedFunction & OF) const1094 void RISCVInstrInfo::buildOutlinedFrame(
1095     MachineBasicBlock &MBB, MachineFunction &MF,
1096     const outliner::OutlinedFunction &OF) const {
1097 
1098   // Strip out any CFI instructions
1099   bool Changed = true;
1100   while (Changed) {
1101     Changed = false;
1102     auto I = MBB.begin();
1103     auto E = MBB.end();
1104     for (; I != E; ++I) {
1105       if (I->isCFIInstruction()) {
1106         I->removeFromParent();
1107         Changed = true;
1108         break;
1109       }
1110     }
1111   }
1112 
1113   MBB.addLiveIn(RISCV::X5);
1114 
1115   // Add in a return instruction to the end of the outlined frame.
1116   MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
1117       .addReg(RISCV::X0, RegState::Define)
1118       .addReg(RISCV::X5)
1119       .addImm(0));
1120 }
1121 
insertOutlinedCall(Module & M,MachineBasicBlock & MBB,MachineBasicBlock::iterator & It,MachineFunction & MF,const outliner::Candidate & C) const1122 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
1123     Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
1124     MachineFunction &MF, const outliner::Candidate &C) const {
1125 
1126   // Add in a call instruction to the outlined function at the given location.
1127   It = MBB.insert(It,
1128                   BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
1129                       .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
1130                                         RISCVII::MO_CALL));
1131   return It;
1132 }
1133 
1134 // clang-format off
1135 #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)                                \
1136   RISCV::PseudoV##OP##_##TYPE##_##LMUL##_COMMUTABLE
1137 
1138 #define CASE_VFMA_OPCODE_LMULS(OP, TYPE)                                       \
1139   CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8):                                      \
1140   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4):                                 \
1141   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2):                                 \
1142   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1):                                  \
1143   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2):                                  \
1144   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4):                                  \
1145   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
1146 
1147 #define CASE_VFMA_SPLATS(OP)                                                   \
1148   CASE_VFMA_OPCODE_LMULS(OP, VF16):                                            \
1149   case CASE_VFMA_OPCODE_LMULS(OP, VF32):                                       \
1150   case CASE_VFMA_OPCODE_LMULS(OP, VF64)
1151 // clang-format on
1152 
findCommutedOpIndices(const MachineInstr & MI,unsigned & SrcOpIdx1,unsigned & SrcOpIdx2) const1153 bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1154                                            unsigned &SrcOpIdx1,
1155                                            unsigned &SrcOpIdx2) const {
1156   const MCInstrDesc &Desc = MI.getDesc();
1157   if (!Desc.isCommutable())
1158     return false;
1159 
1160   switch (MI.getOpcode()) {
1161   case CASE_VFMA_SPLATS(FMADD):
1162   case CASE_VFMA_SPLATS(FMSUB):
1163   case CASE_VFMA_SPLATS(FMACC):
1164   case CASE_VFMA_SPLATS(FMSAC):
1165   case CASE_VFMA_SPLATS(FNMADD):
1166   case CASE_VFMA_SPLATS(FNMSUB):
1167   case CASE_VFMA_SPLATS(FNMACC):
1168   case CASE_VFMA_SPLATS(FNMSAC):
1169   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1170   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1171   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1172   case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
1173     // For these instructions we can only swap operand 1 and operand 3 by
1174     // changing the opcode.
1175     unsigned CommutableOpIdx1 = 1;
1176     unsigned CommutableOpIdx2 = 3;
1177     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
1178                               CommutableOpIdx2))
1179       return false;
1180     return true;
1181   }
1182   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1183   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1184   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1185   case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
1186     // For these instructions we have more freedom. We can commute with the
1187     // other multiplicand or with the addend/subtrahend/minuend.
1188 
1189     // Any fixed operand must be from source 1, 2 or 3.
1190     if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3)
1191       return false;
1192     if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3)
1193       return false;
1194 
1195     // It both ops are fixed one must be the tied source.
1196     if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1197         SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx1 != 1 && SrcOpIdx2 != 1)
1198       return false;
1199 
1200     // Look for two different register operands assumed to be commutable
1201     // regardless of the FMA opcode. The FMA opcode is adjusted later if
1202     // needed.
1203     if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1204         SrcOpIdx2 == CommuteAnyOperandIndex) {
1205       // At least one of operands to be commuted is not specified and
1206       // this method is free to choose appropriate commutable operands.
1207       unsigned CommutableOpIdx1 = SrcOpIdx1;
1208       if (SrcOpIdx1 == SrcOpIdx2) {
1209         // Both of operands are not fixed. Set one of commutable
1210         // operands to the tied source.
1211         CommutableOpIdx1 = 1;
1212       } else if (SrcOpIdx1 == CommutableOpIdx1) {
1213         // Only one of the operands is not fixed.
1214         CommutableOpIdx1 = SrcOpIdx2;
1215       }
1216 
1217       // CommutableOpIdx1 is well defined now. Let's choose another commutable
1218       // operand and assign its index to CommutableOpIdx2.
1219       unsigned CommutableOpIdx2;
1220       if (CommutableOpIdx1 != 1) {
1221         // If we haven't already used the tied source, we must use it now.
1222         CommutableOpIdx2 = 1;
1223       } else {
1224         Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg();
1225 
1226         // The commuted operands should have different registers.
1227         // Otherwise, the commute transformation does not change anything and
1228         // is useless. We use this as a hint to make our decision.
1229         if (Op1Reg != MI.getOperand(2).getReg())
1230           CommutableOpIdx2 = 2;
1231         else
1232           CommutableOpIdx2 = 3;
1233       }
1234 
1235       // Assign the found pair of commutable indices to SrcOpIdx1 and
1236       // SrcOpIdx2 to return those values.
1237       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
1238                                 CommutableOpIdx2))
1239         return false;
1240     }
1241 
1242     return true;
1243   }
1244   }
1245 
1246   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1247 }
1248 
1249 #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)               \
1250   case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_COMMUTABLE:                   \
1251     Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_COMMUTABLE;                \
1252     break;
1253 
1254 #define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)                      \
1255   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8)                      \
1256   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4)                      \
1257   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2)                      \
1258   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1)                       \
1259   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2)                       \
1260   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4)                       \
1261   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
1262 
1263 #define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)                           \
1264   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF16)                            \
1265   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF32)                            \
1266   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF64)
1267 
commuteInstructionImpl(MachineInstr & MI,bool NewMI,unsigned OpIdx1,unsigned OpIdx2) const1268 MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
1269                                                      bool NewMI,
1270                                                      unsigned OpIdx1,
1271                                                      unsigned OpIdx2) const {
1272   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1273     if (NewMI)
1274       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1275     return MI;
1276   };
1277 
1278   switch (MI.getOpcode()) {
1279   case CASE_VFMA_SPLATS(FMACC):
1280   case CASE_VFMA_SPLATS(FMADD):
1281   case CASE_VFMA_SPLATS(FMSAC):
1282   case CASE_VFMA_SPLATS(FMSUB):
1283   case CASE_VFMA_SPLATS(FNMACC):
1284   case CASE_VFMA_SPLATS(FNMADD):
1285   case CASE_VFMA_SPLATS(FNMSAC):
1286   case CASE_VFMA_SPLATS(FNMSUB):
1287   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1288   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1289   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1290   case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
1291     // It only make sense to toggle these between clobbering the
1292     // addend/subtrahend/minuend one of the multiplicands.
1293     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
1294     assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
1295     unsigned Opc;
1296     switch (MI.getOpcode()) {
1297       default:
1298         llvm_unreachable("Unexpected opcode");
1299       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD)
1300       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC)
1301       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSAC, FMSUB)
1302       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSUB, FMSAC)
1303       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMACC, FNMADD)
1304       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC)
1305       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB)
1306       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC)
1307       CASE_VFMA_CHANGE_OPCODE_LMULS(FMACC, FMADD, VV)
1308       CASE_VFMA_CHANGE_OPCODE_LMULS(FMSAC, FMSUB, VV)
1309       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMACC, FNMADD, VV)
1310       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSAC, FNMSUB, VV)
1311     }
1312 
1313     auto &WorkingMI = cloneIfNew(MI);
1314     WorkingMI.setDesc(get(Opc));
1315     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1316                                                    OpIdx1, OpIdx2);
1317   }
1318   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1319   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1320   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1321   case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
1322     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
1323     // If one of the operands, is the addend we need to change opcode.
1324     // Otherwise we're just swapping 2 of the multiplicands.
1325     if (OpIdx1 == 3 || OpIdx2 == 3) {
1326       unsigned Opc;
1327       switch (MI.getOpcode()) {
1328         default:
1329           llvm_unreachable("Unexpected opcode");
1330         CASE_VFMA_CHANGE_OPCODE_LMULS(FMADD, FMACC, VV)
1331         CASE_VFMA_CHANGE_OPCODE_LMULS(FMSUB, FMSAC, VV)
1332         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMADD, FNMACC, VV)
1333         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSUB, FNMSAC, VV)
1334       }
1335 
1336       auto &WorkingMI = cloneIfNew(MI);
1337       WorkingMI.setDesc(get(Opc));
1338       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1339                                                      OpIdx1, OpIdx2);
1340     }
1341     // Let the default code handle it.
1342     break;
1343   }
1344   }
1345 
1346   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1347 }
1348 
1349 #undef CASE_VFMA_CHANGE_OPCODE_SPLATS
1350 #undef CASE_VFMA_CHANGE_OPCODE_LMULS
1351 #undef CASE_VFMA_CHANGE_OPCODE_COMMON
1352 #undef CASE_VFMA_SPLATS
1353 #undef CASE_VFMA_OPCODE_LMULS
1354 #undef CASE_VFMA_OPCODE_COMMON
1355 
getVLENFactoredAmount(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator II,const DebugLoc & DL,int64_t Amount) const1356 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
1357                                                MachineBasicBlock &MBB,
1358                                                MachineBasicBlock::iterator II,
1359                                                const DebugLoc &DL,
1360                                                int64_t Amount) const {
1361   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
1362   assert(Amount % 8 == 0 &&
1363          "Reserve the stack by the multiple of one vector size.");
1364 
1365   MachineRegisterInfo &MRI = MF.getRegInfo();
1366   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
1367   int64_t NumOfVReg = Amount / 8;
1368 
1369   Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1370   BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
1371   assert(isInt<12>(NumOfVReg) &&
1372          "Expect the number of vector registers within 12-bits.");
1373   if (isPowerOf2_32(NumOfVReg)) {
1374     uint32_t ShiftAmount = Log2_32(NumOfVReg);
1375     if (ShiftAmount == 0)
1376       return VL;
1377     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
1378         .addReg(VL, RegState::Kill)
1379         .addImm(ShiftAmount);
1380   } else {
1381     Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1382     BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N)
1383         .addReg(RISCV::X0)
1384         .addImm(NumOfVReg);
1385     if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
1386       MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
1387           MF.getFunction(),
1388           "M-extension must be enabled to calculate the vscaled size/offset."});
1389     BuildMI(MBB, II, DL, TII->get(RISCV::MUL), VL)
1390         .addReg(VL, RegState::Kill)
1391         .addReg(N, RegState::Kill);
1392   }
1393 
1394   return VL;
1395 }
1396 
1397 Optional<std::pair<unsigned, unsigned>>
isRVVSpillForZvlsseg(unsigned Opcode) const1398 RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
1399   switch (Opcode) {
1400   default:
1401     return None;
1402   case RISCV::PseudoVSPILL2_M1:
1403   case RISCV::PseudoVRELOAD2_M1:
1404     return std::make_pair(2u, 1u);
1405   case RISCV::PseudoVSPILL2_M2:
1406   case RISCV::PseudoVRELOAD2_M2:
1407     return std::make_pair(2u, 2u);
1408   case RISCV::PseudoVSPILL2_M4:
1409   case RISCV::PseudoVRELOAD2_M4:
1410     return std::make_pair(2u, 4u);
1411   case RISCV::PseudoVSPILL3_M1:
1412   case RISCV::PseudoVRELOAD3_M1:
1413     return std::make_pair(3u, 1u);
1414   case RISCV::PseudoVSPILL3_M2:
1415   case RISCV::PseudoVRELOAD3_M2:
1416     return std::make_pair(3u, 2u);
1417   case RISCV::PseudoVSPILL4_M1:
1418   case RISCV::PseudoVRELOAD4_M1:
1419     return std::make_pair(4u, 1u);
1420   case RISCV::PseudoVSPILL4_M2:
1421   case RISCV::PseudoVRELOAD4_M2:
1422     return std::make_pair(4u, 2u);
1423   case RISCV::PseudoVSPILL5_M1:
1424   case RISCV::PseudoVRELOAD5_M1:
1425     return std::make_pair(5u, 1u);
1426   case RISCV::PseudoVSPILL6_M1:
1427   case RISCV::PseudoVRELOAD6_M1:
1428     return std::make_pair(6u, 1u);
1429   case RISCV::PseudoVSPILL7_M1:
1430   case RISCV::PseudoVRELOAD7_M1:
1431     return std::make_pair(7u, 1u);
1432   case RISCV::PseudoVSPILL8_M1:
1433   case RISCV::PseudoVRELOAD8_M1:
1434     return std::make_pair(8u, 1u);
1435   }
1436 }
1437