| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 507 SDValue LL, LH, RL, RH, CL, CH; SplitRes_Select() local
556 SDValue LL, LH, RL, RH; SplitRes_SELECT_CC() local
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| H A D | LegalizeIntegerTypes.cpp | 4263 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
4127 SDValue LL, LH, RL, RH; ExpandIntRes_Logical() local
4140 SDValue LL, LH, RL, RH; ExpandIntRes_MUL() local
[all...] |
| H A D | LegalizeVectorTypes.cpp | 2388 SDValue LL, LH, RL, RH; SplitVecRes_SETCC() local
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| H A D | TargetLowering.cpp | 10436 forceExpandWideMUL(SelectionDAG & DAG,const SDLoc & dl,bool Signed,EVT WideVT,const SDValue LL,const SDValue LH,const SDValue RL,const SDValue RH,SDValue & Lo,SDValue & Hi) const forceExpandWideMUL() argument
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1734 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1832 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf() argument
[all...] |
| H A D | HexagonConstPropagation.cpp | 2515 evaluateHexRSEQ32(RegisterSubReg RL,RegisterSubReg RH,const CellMap & Inputs,LatticeCell & Result) evaluateHexRSEQ32() argument
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| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 667 SDValue LH, RH; in TryExpandADDWithMul() local
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| /llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LowerMatrixIntrinsics.cpp | 1561 Value *RH = Builder.CreateExtractElement( emitMatrixMultiply() local
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4151 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); lowerSMUL_LOHI() local
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