1 /* $NetBSD: mcp23xxxgpioreg.h,v 1.1 2022/01/17 16:31:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank Kardel, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_IC_MCP23xxxGPIOREG_H_ 33 #define _DEV_IC_MCP23xxxGPIOREG_H_ 34 35 /* 36 * Microchip serial I/O expanders: 37 * 38 * MCP23008 8-bit, I2C interface 39 * MCP23S08 8-bit, SPI interface 40 * MCP23017 16-bit, I2C interface 41 * MCP23S17 16-bit, SPI interface 42 * MCP23018 16-bit (open-drain outputs), I2C interface 43 * MCP23S18 16-bit (open-drain outputs), SPI interface 44 * 45 * Data sheet: 46 * 47 * https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf 48 */ 49 50 /* resources */ 51 #define MCPGPIO_PINS_PER_BANK 8 52 53 #define MCP23x08_GPIO_NBANKS 1 54 #define MCP23x08_GPIO_NPINS (MCPGPIO_PINS_PER_BANK * MCP23x08_GPIO_NBANKS) 55 56 #define MCP23x17_GPIO_NBANKS 2 57 #define MCP23x17_GPIO_NPINS (MCPGPIO_PINS_PER_BANK * MCP23x17_GPIO_NBANKS) 58 59 /* 60 * The MCP23x17 has two addressing schemes, depending on the setting 61 * of IOCON.BANK: 62 * 63 * IOCON.BANK=1 IOCON.BANK=0 Register 64 * ----------------------------------------------------- 65 * 0x00 0x00 IODIRA 66 * 0x10 0x01 IODIRB 67 * 0x01 0x02 IPOLA 68 * 0x11 0x03 IPOLB 69 * 0x02 0x04 GPINTENA 70 * 0x12 0x05 GPINTENB 71 * 0x03 0x06 DEFVALA 72 * 0x13 0x07 DEFVALB 73 * 0x04 0x08 INTCONA 74 * 0x14 0x09 INTCONB 75 * 0x05 0x0a IOCON 76 * 0x15 0x0b IOCON (yes, it's an alias) 77 * 0x06 0x0c GPPUA 78 * 0x16 0x0d GPPUB 79 * 0x07 0x0e INTFA 80 * 0x17 0x0f INTFB 81 * 0x08 0x10 INTCAPA 82 * 0x18 0x11 INTCAPB 83 * 0x09 0x12 GPIOA 84 * 0x19 0x13 GPIOB 85 * 0x0a 0x14 OLATA 86 * 0x1a 0x15 OLATB 87 * 88 * The MCP23x08, of course, only has a single bank of 8 GPIOs, and it 89 * has an addressing schme that operates like IOCON.BANK=1 90 */ 91 #define REG_IODIR 0x00 92 #define REG_IPOL 0x01 93 #define REG_GPINTEN 0x02 94 #define REG_DEFVAL 0x03 95 #define REG_INTCON 0x04 96 #define REG_IOCON 0x05 97 #define REG_GPPU 0x06 98 #define REG_INTF 0x07 99 #define REG_INTCAP 0x08 100 #define REG_GPIO 0x09 101 #define REG_OLAT 0x0a 102 103 /* IOCON.BANK=1 */ 104 #define REGADDR_BANK1(bank, reg) (((bank) << 4) | (reg)) 105 106 /* IOCON.BANK=0 */ 107 #define REGADDR_BANK0(bank, reg) (((reg) << 1) | (bank)) 108 109 /* bits */ 110 #define IOCON_BANK __BIT(7) /* select address layout (23x1x only) */ 111 #define IOCON_MIRROR __BIT(6) /* mirror INTA/INTB outputs (23x1x only) */ 112 #define IOCON_SEQOP __BIT(5) /* sequential address operation */ 113 #define IOCON_DISLW __BIT(4) /* slew rate SDA output */ 114 #define IOCON_HAEN __BIT(3) /* hardware address enable bit (SPI only) */ 115 #define IOCON_ODR __BIT(2) /* configure INT pin as open drain */ 116 #define IOCON_INTPOL __BIT(1) /* INT pin polarity (unless ODR is set) */ 117 118 #endif /* _DEV_IC_MCP23xxxGPIOREG_H_ */ 119