Searched defs:RCID (Results 1 – 10 of 10) sorted by relevance
191 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
4887 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass()4963 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local4972 unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass; in legalizeOpWithMove() local7896 const auto RCID = MI.getDesc().operands()[Idx].RegClass; in isBufferSMRD() local
378 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
913 unsigned RCID; in getRegClassConstraint() local1747 unsigned RCID = 0; in print() local
1515 unsigned RCID = 0; in createMIROperandComment() local
674 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local761 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
1596 unsigned RCID; in handleSpecialFP() local
264 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline()268 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods()407 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()2648 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2208 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()2356 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
181 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local