Searched defs:RCID (Results 1 – 10 of 10) sorted by relevance
203 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
5423 adjustAllocatableRegClass(const GCNSubtarget & ST,const SIRegisterInfo & RI,const MachineRegisterInfo & MRI,const MCInstrDesc & TID,unsigned RCID,bool IsAllocatable) adjustAllocatableRegClass() argument 5499 unsigned RCID = Desc.operands()[OpNo].RegClass; getOpRegClass() local 5508 unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass; legalizeOpWithMove() local 8913 const auto RCID = MI.getDesc().operands()[Idx].RegClass; isBufferSMRD() local [all...]
371 unsigned RCID = N->getConstantOperandVal(0); getOperandRegClass() local
754 int RCID = Desc.operands()[OpNo].RegClass; printRegularOperand() local 831 int RCID = Desc.operands()[OpNo].RegClass; printRegularOperand() local
1594 unsigned RCID; handleSpecialFP() local
929 unsigned RCID; getRegClassConstraint() local 1774 unsigned RCID; print() local
1706 unsigned RCID; createMIROperandComment() local
269 isRegOrInline(unsigned RCID,MVT type) const isRegOrInline() argument 273 isRegOrImmWithInputMods(unsigned RCID,MVT type) const isRegOrImmWithInputMods() argument 416 isRegOrInlineNoMods(unsigned RCID,MVT type) const isRegOrInlineNoMods() argument 2686 int RCID = getRegClass(RegKind, RegWidth); getRegularReg() local [all...]
2429 getRegBitWidth(unsigned RCID) getRegBitWidth() argument 2575 unsigned RCID = Desc.operands()[OpNo].RegClass; getRegOperandSize() local
215 unsigned RCID = getRegClassIDForVecVT(ContainerVT); RISCVTargetLowering() local