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Searched defs:RC (Results 1 – 25 of 279) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
289 -> BT::RegisterCell { in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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H A DHexagonConstPropagation.cpp719 LatticeCell RC = Cells.get(DefR.Reg); in visitNonBranch() local
1087 LatticeCell &RC) { in getCell()
1397 LatticeCell RC; in evaluateANDrr() local
1413 LatticeCell RC; in evaluateANDri() local
1464 LatticeCell RC; in evaluateORrr() local
1480 LatticeCell RC; in evaluateORri() local
1529 LatticeCell RC; in evaluateXORrr() local
1948 LatticeCell RC; in evaluate() local
1970 LatticeCell RC; in evaluate() local
2004 LatticeCell RC = Outputs.get(DefR.Reg); in evaluate() local
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H A DHexagonBitSimplify.cpp330 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
339 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
409 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); in getSubregMask() local
901 auto *RC = MRI.getRegClass(RR.Reg); in getFinalVRegClass() local
907 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
1262 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI); in computeUsedBits() local
1413 Register ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, in genTfrConst()
1559 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch() local
1696 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
1706 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h76 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
92 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
109 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
125 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
133 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
H A DTargetRegisterInfo.h119 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
124 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
131 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
136 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
274 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
280 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
286 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
291 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
299 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
313 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
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H A DExecutionDomainFix.h120 const TargetRegisterClass *const RC; variable
139 ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC) in ExecutionDomainFix()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
107 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
126 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
145 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
164 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
273 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
306 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
378 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp73 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
171 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses()
223 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
230 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
246 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); in emitBaseClassImplementation() local
288 for (const CodeGenRegisterClass *RC : in run() local
292 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
H A DRegisterInfoEmitter.cpp146 for (const auto &RC : RegisterClasses) in runEnums() local
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
1041 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1078 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1190 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1227 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1240 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1284 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1328 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1356 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
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H A DCodeGenRegisters.cpp944 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
968 for (auto &RC : RegClasses) { in computeSubClasses() local
984 for (auto &RC : RegClasses) in computeSubClasses() local
1012 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs() local
1022 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs() local
1201 CodeGenRegisterClass &RC = RegClasses.back(); in CodeGenRegBank() local
1212 for (auto &RC : RegClasses) in CodeGenRegBank() local
1247 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1259 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1275 if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) in getRegClass() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h154 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
166 bool isAGPRClass(const TargetRegisterClass *RC) const { in isAGPRClass()
177 bool hasVectorRegisters(const TargetRegisterClass *RC) const { in hasVectorRegisters()
237 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp71 const TargetRegisterClass *RC; in initGlobalBaseReg() local
152 const TargetRegisterClass &RC = in createEhDataRegsFI() local
167 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
194 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
H A DMipsSEFrameLowering.cpp173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
833 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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H A DMipsInstrInfo.h119 const TargetRegisterClass *RC, in storeRegToStackSlot()
127 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp451 const TargetRegisterClass *RC, in PPCEmitLoad()
608 const TargetRegisterClass *RC = in SelectLoad() local
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
987 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1050 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1129 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1173 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1224 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1279 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1441 const TargetRegisterClass *RC = in processCallArgs() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveStacks.cpp57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
H A DTargetRegisterInfo.cpp218 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass() local
236 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT() local
248 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
352 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
503 const TargetRegisterClass *RC{}; in getRegSizeInBits() local
524 const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, in getCoveringSubRegIndexes()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp28 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
72 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIRBuilder.h1147 auto *RC = dyn_cast<Constant>(R); in foldConstant() local
1193 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1210 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1227 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1244 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1258 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1282 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1303 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1323 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1341 if (auto *RC = dyn_cast<Constant>(RHS)) { variable
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp63 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
364 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
368 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
482 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
493 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp81 const TargetRegisterClass *RC, in storeRegToStackSlot()
109 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp710 unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, in getLoadStoreRegOpcode()
732 unsigned getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, in getStoreRegOpcode()
738 unsigned getLoadRegOpcode(unsigned DstReg, const TargetRegisterClass *RC, in getLoadRegOpcode()
745 bool M68kInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, in getStackSlotRange()
759 const TargetRegisterClass *RC, in storeRegToStackSlot()
774 const TargetRegisterClass *RC, in loadRegFromStackSlot()

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