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Searched defs:PredReg (Results 1 – 21 of 21) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp73 Register PredReg; in ReplaceTailWithBranchTo() local
121 Register PredReg; in isLegalToSplitMBBAt() local
279 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
539 Register PredReg; in rewriteT2FrameIndex() local
754 Register &PredReg) { in getITInstrPredicate()
775 Register &PredReg) { in getVPTInstrPredicate()
H A DThumb2InstrInfo.h86 Register PredReg; in getVPTInstrPredicate() local
H A DARMLoadStoreOptimizer.cpp488 unsigned PredReg) { in UpdateBaseRegUses()
628 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
835 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
905 Register PredReg; in MergeOpsUpdate() local
1189 ARMCC::CondCodes Pred, Register PredReg) { in isIncrementOrDecrement()
1221 ARMCC::CondCodes Pred, Register PredReg, int &Offset) { in findIncDecBefore()
1241 ARMCC::CondCodes Pred, Register PredReg, int &Offset, in findIncDecAfter()
1294 Register PredReg; in MergeBaseUpdateLSMultiple() local
1490 Register PredReg; in MergeBaseUpdateLoadStore() local
1628 Register PredReg; in MergeBaseUpdateLSDouble() local
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H A DMVEVPTBlockPass.cpp106 Register PredReg; in StepOverPredicatedInstrs() local
240 Register PredReg; in InsertVPTBlocks() local
H A DThumb2SizeReduction.cpp471 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
689 Register PredReg; in ReduceSpecial() local
731 Register PredReg; in ReduceSpecial() local
802 Register PredReg; in ReduceTo2Addr() local
895 Register PredReg; in ReduceToNarrow() local
H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
H A DThumb2ITBlockPass.cpp202 Register PredReg; in InsertITInstructions() local
H A DARMBaseRegisterInfo.cpp480 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
829 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
H A DARMConstantIslandPass.cpp1410 Register PredReg; in createNewWater() local
1456 Register PredReg; in createNewWater() local
1480 Register PredReg; in createNewWater() local
1885 Register PredReg; in optimizeThumb2Branches() local
H A DARMFrameLowering.cpp244 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
258 unsigned PredReg = 0) { in emitSPUpdate()
2315 unsigned PredReg = TII.getFramePred(Old); in eliminateCallFramePseudoInstr() local
H A DARMISelDAGToDAG.cpp1737 SDValue PredReg; in tryMVEIndexedLoad() local
2883 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
4066 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4089 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4111 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
H A DARMBaseInstrInfo.cpp2221 Register &PredReg) { in getInstrPredicate()
2251 Register PredReg; in commuteInstructionImpl() local
2456 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate()
5499 Register PredReg; in findCMPToFoldIntoCBZ() local
H A DARMExpandPseudoInsts.cpp888 Register PredReg; in ExpandMOV32BitImm() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
91 unsigned PredReg = Hexagon::NoRegister; in init() local
H A DHexagonMCCompound.cpp177 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp323 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred()
H A DHexagonInstrInfo.cpp1614 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
4442 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg()
H A DHexagonHardwareLoops.cpp648 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1306 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr()