1 /* $NetBSD: plumvideoreg.h,v 1.7 2024/05/23 08:30:51 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* (CS3) */ 33 #define PLUM_VIDEO_REGBASE 0x1000 34 #define PLUM_VIDEO_REGSIZE 0x200 35 36 /* (MCS0) */ 37 /* VRAM 4MByte */ 38 #define PLUM_VIDEO_VRAM_IOBASE_PHYSICAL 0x6c000000 39 #define PLUM_VIDEO_VRAM_IOBASE 0x00000000 40 #define PLUM_VIDEO_VRAM_IOSIZE 0x00400000 41 /* Color palette LCD 4KByte */ 42 #define PLUM_VIDEO_CLUT_LCD_IOBASE 0x00400000 43 #define PLUM_VIDEO_CLUT_LCD_IOSIZE 0x00001000 44 /* Color palette CRT 4KByte */ 45 #define PLUM_VIDEO_CLUT_CRT_IOBASE 0x00401000 46 #define PLUM_VIDEO_CLUT_CRT_IOSIZE 0x00001000 47 /* BitBlt 4KByte */ 48 #define PLUM_VIDEO_BITBLT_IOBASE 0x00402000 49 #define PLUM_VIDEO_BITBLT_IOSIZE 0x00401000 50 51 /* 52 * Common Control Register 53 */ 54 /* Interrupt Status enable and IRQ line enable */ 55 #define PLUM_VIDEO_POSENIEN_REG 0x000 56 /* Interrupt Status */ 57 #define PLUM_VIDEO_POIST_REG 0x004 58 /* Buffer Control */ 59 #define PLUM_VIDEO_POBFC_REG 0x008 60 /* VRAM Control */ 61 #define PLUM_VIDEO_PORAM_REG 0x00c 62 /* VRAM Refresh Control */ 63 #define PLUM_VIDEO_POREF_REG 0x010 64 /* LCD Clock Source select and control */ 65 #define PLUM_VIDEO_POCKL_REG 0x014 66 /* CRT Clock Source select and control */ 67 #define PLUM_VIDEO_POCKC_REG 0x018 68 /* PLL Clock Source select and control */ 69 #define PLUM_VIDEO_POPLL_REG 0x01c 70 71 /* 72 * LCD Panel Control Register 73 */ 74 /* LCD Control */ 75 #define PLUM_VIDEO_PLCNT_REG 0x040 76 /* STN Control */ 77 #define PLUM_VIDEO_PLSTN_REG 0x044 78 /* LCD Level control */ 79 #define PLUM_VIDEO_PLLEV_REG 0x048 80 /* LCD Luminance control */ 81 #define PLUM_VIDEO_PLLUM_REG 0x04c 82 #define PLUM_VIDEO_PLLUM_MAX 0x3 83 #define PLUM_VIDEO_PLLUM_MIN 0x0 84 /* DSTN Dither Pattern base address */ 85 #define PLUM_VIDEO_PLDPA_REG 0x050 86 /* DSTN VRAM Offscreen buffer address */ 87 #define PLUM_VIDEO_PLOSA_REG 0x054 88 89 /* 90 * CRT Control Register 91 */ 92 /* DAC Control */ 93 #define PLUM_VIDEO_PCDAC_REG 0x060 94 /* CRT Border Color */ 95 #define PLUM_VIDEO_PCBOC_REG 0x064 96 /* Palette snoop */ 97 #define PLUM_VIDEO_PCSNP_REG 0x068 98 99 /* 100 * LCD Timing Register 101 */ 102 /* Horizontal Total */ 103 #define PLUM_VIDEO_PLHT_REG 0x080 104 /* Horizontal Display Start */ 105 #define PLUM_VIDEO_PLHDS_REG 0x084 106 /* H-Sync Start/End */ 107 #define PLUM_VIDEO_PLHSEHSS_REG 0x088 108 /* H-Blanking Start/End */ 109 #define PLUM_VIDEO_PLHBEHSS_REG 0x08c 110 /* Horizontal # of pixel */ 111 #define PLUM_VIDEO_PLHPX_REG 0x090 112 /* Vertical Total */ 113 #define PLUM_VIDEO_PLVT_REG 0x094 114 /* Vertical Display Start */ 115 #define PLUM_VIDEO_PLVDS_REG 0x098 116 /* V-Sync Start/End */ 117 #define PLUM_VIDEO_PLVSEVSS_REG 0x09c 118 /* V-Blanking Start/End */ 119 #define PLUM_VIDEO_PLVBEVBS_REG 0x0a0 120 /* Current Line # */ 121 #define PLUM_VIDEO_PLCLN_REG 0x0a8 122 /* Interrupt Line # */ 123 #define PLUM_VIDEO_PLILN_REG 0x0ac 124 /* Mode */ 125 #define PLUM_VIDEO_PLMOD_REG 0x0b0 126 /* LCD controller test */ 127 #define PLUM_VIDEO_PLTST_REG 0x0bc 128 129 /* 130 * LCD Graphics Register 131 */ 132 /* Double Buffer Select */ 133 #define PLUM_VIDEO_PLBSL_REG 0x0c0 134 /* Graphics Display Start Address */ 135 #define PLUM_VIDEO_PLDSA0_REG 0x0c4 136 #define PLUM_VIDEO_PLDSA1_REG 0x0c8 137 /* VRAM Pitch 1 */ 138 #define PLUM_VIDEO_PLPIT1_REG 0x0cc 139 /* VRAM Pitch 2 */ 140 #define PLUM_VIDEO_PLPIT2_REG 0x0d0 141 #define PLUM_VIDEO_PLPIT2_MASK 0xffffffe0 142 /* VRAM Offset */ 143 #define PLUM_VIDEO_PLOFS_REG 0x0d4 144 /* VRAM Lower Screen Address offset */ 145 #define PLUM_VIDEO_PLLSA_REG 0x0d8 146 /* Graphics Mode */ 147 #define PLUM_VIDEO_PLGMD_REG 0x0dc 148 149 #define PLUM_VIDEO_PLGMD_GMODE_MASK 0x3 150 #define PLUM_VIDEO_PLGMD_DISABLE 0x0 151 #define PLUM_VIDEO_PLGMD_8BPP 0x1 152 #define PLUM_VIDEO_PLGMD_16BPP 0x2 153 154 #define PLUM_VIDEO_PLGMD_MODE_DISPLAY 0x4 155 #define PLUM_VIDEO_PLGMD_PALETTE_ENABLE 0x8 156 157 /* 158 * CRT Timing Register 159 */ 160 /* notyet */ 161 /* 162 * CRT Graphics Register 163 */ 164 /* notyet */ 165