1 /* $NetBSD: plumicureg.h,v 1.5 2022/05/31 11:22:33 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PLUM2 INTERRUPT CONTROLLER UNIT 34 */ 35 #define PLUM_INT_REGBASE 0x8000 36 #define PLUM_INT_REGSIZE 0x1000 37 38 /* 39 * Interrupt status register 40 */ 41 #define PLUM_INT_INTSTA_REG 0x000 42 #define PLUM_INT_INTSTA_EXTINT 0x00000080 43 #define PLUM_INT_INTSTA_SMINT 0x00000040 44 #define PLUM_INT_INTSTA_USBWAKE 0x00000020 45 #define PLUM_INT_INTSTA_USBINT 0x00000010 46 #define PLUM_INT_INTSTA_DISPINT 0x00000008 47 #define PLUM_INT_INTSTA_C2SCINT 0x00000004 48 #define PLUM_INT_INTSTA_C1SCINT 0x00000002 49 #define PLUM_INT_INTSTA_PCCINT 0x00000001 50 51 /* 52 * Interrupt enable register 53 */ 54 #define PLUM_INT_INTIEN_REG 0x010 55 #define PLUM_INT_INTIEN 0x00000001 56 57 /* 58 * External interrupts 59 */ 60 /* outside input interrupt status register */ 61 #define PLUM_INT_EXTINTS_REG 0x100 62 63 #define PLUM_INT_EXTINTS_IO3INT1 0x00000020 64 #define PLUM_INT_EXTINTS_IO3INT0 0x00000010 65 #define PLUM_INT_EXTINTS_IO5INT3 0x00000008 66 #define PLUM_INT_EXTINTS_IO5INT2 0x00000004 67 #define PLUM_INT_EXTINTS_IO5INT1 0x00000002 68 #define PLUM_INT_EXTINTS_IO5INT0 0x00000001 69 70 /* outside input interrupt status register (after the mask) */ 71 #define PLUM_INT_EXTINTM_REG 0x104 72 73 /* interrupt enable register from the outside input */ 74 #define PLUM_INT_EXTIEN_REG 0x110 75 76 #define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020 77 #define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010 78 #define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008 79 #define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004 80 #define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002 81 #define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001 82 83 #define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000 84 #define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000 85 #define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800 86 #define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400 87 #define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200 88 #define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100 89 90 /* 91 * PC-card interrupts 92 */ 93 /* PC-card interrupt status register */ 94 #define PLUM_INT_PCCINTS_REG 0x200 95 96 #define PLUM_INT_PCCINTS_C2RI 0x00000008 97 #define PLUM_INT_PCCINTS_C2IO 0x00000004 98 #define PLUM_INT_PCCINTS_C1RI 0x00000002 99 #define PLUM_INT_PCCINTS_C1IO 0x00000001 100 101 /* PC-card interrupt status register (masked) */ 102 #define PLUM_INT_PCCINTM_REG 0x204 103 /* PC-card interrupt enable register */ 104 #define PLUM_INT_PCCIEN_REG 0x210 105 106 #define PLUM_INT_PCCIEN_SENC2RI 0x00000800 107 #define PLUM_INT_PCCIEN_SENC2IO 0x00000400 108 #define PLUM_INT_PCCIEN_SENC1RI 0x00000200 109 #define PLUM_INT_PCCIEN_SENC1IO 0x00000100 110 #define PLUM_INT_PCCIEN_IENC2RI 0x00000008 111 #define PLUM_INT_PCCIEN_IENC2IO 0x00000004 112 #define PLUM_INT_PCCIEN_IENC1RI 0x00000002 113 #define PLUM_INT_PCCIEN_IENC1IO 0x00000001 114 115 /* PC-card interrupt detection register */ 116 #define PLUM_INT_PCCLKSL_REG 0x220 117 #define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/ 118 119 /* 120 * USB interrupts 121 */ 122 /* USB interrupt enable register */ 123 #define PLUM_INT_USBINTEN_REG 0x310 124 125 /* master-enables the USB interrupts */ 126 #define PLUM_INT_USBINTEN_IEN 0x00000002 127 /* enables the clock restart request interrupts */ 128 #define PLUM_INT_USBINTEN_WIEN 0x00000001 129 130 /* 131 * SmartMedia interrupts 132 */ 133 /* SmartMedia interrupt enable register */ 134 #define PLUM_INT_SMIEN_REG 0x410 135 136 #define PLUM_INT_SMIEN 0x00000001 137